AD7734 Analog Devices, AD7734 Datasheet
AD7734
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AD7734 Summary of contents
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... Other parts in the AD7734 family are the AD7732 and the AD7738. The AD7732 is similar to AD7734, but its analog front end features two fully differential input channels. The AD7738 analog front end is configurable for four fully differential or eight single-ended input channels, features 0 ...
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... Channel Conversion Time Registers ....................................... 19 REVISION HISTORY Revision 0: Initial Version Mode Register ............................................................................. 20 Digital Interface Description ........................................................ 22 Hardware ..................................................................................... 22 Reset ............................................................................................. 23 Access the AD7734 Registers.................................................... 23 Single Conversion and Reading Data ...................................... 23 Dump Mode................................................................................ 24 Continuous Conversion Mode ................................................. 24 Continuous Read (Continuous Conversion) Mode .............. 25 Circuit Description......................................................................... 26 Analog Front End....................................................................... 26 Analog Input’s Extended Voltage Range ................................. 27 Chopping ...
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... FW ≥ 8 (Conversion Time ≥ 117 µ FSR mV Before Calibration µV/°C % Before Calibration ppm of FS/° FSR Before Calibration ppm of FS/° FSR After Calibration LSB At DC, AIN = ± DC, Maximum ±16.5 V AIN Voltage kΩ kΩ AD7734 ...
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... AD7734 Parameter 1, 8 BIAS0 to 3, BIASHI Pin Impedance Input Resistor Matching Input Resistor Temp. Coefficient REFERENCE INPUTS 1, 9 REFIN(+) to REFIN(–) Voltage NOREF Trigger Voltage REFIN(+), REFIN(–) 1 Common-Mode Voltage 10 Reference Input DC Current 1, 11 SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration Limit ...
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... These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register External MCLKIN = digital inputs = Min Typ Max 85 100 100 525 . REF , P0 and Rev Page Unit Test Conditions/Comments mW µA µW AD7734 ...
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... AD7734 TIMING SPECIFICATIONS Table 2. ( ± ± 5%; Input Logic Logic unless otherwise noted.) Parameter Min Master Clock Range 500 2 Read Operation ...
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... Figure 3. Write Cycle Timing Diagram TO OUTPUT PIN 50pF Figure 4. Load Circuit for Access Time and Bus Relinquish Time Rev Page LSB t 16 LSB I (800µ SINK DD 100µ 3V) DD 1.6V I (200µ SOURCE DD 100µ 3V) DD AD7734 ...
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... AD7734 ABSOLUTE MAXIMUM RATINGS Table 25°C, unless otherwise noted. A Parameter AV to AGND DGND DD DD AGND to DGND AIN to AGND BIAS to AGND REFIN+, REFIN– to AGND MUX0, INTBIAS to AGND P0, P1 Voltage to AGND P0, P1 Current (T = 70°C) MAX P0, P1 Current (T = 85° ...
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... AIN DIFFERENTIAL VOLTAGE – V Figure 9. Typical INL vs. AIN Voltage, AIN Range = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = MCLK FREQUENCY – MHz Figure 10. Typical Supply Current vs. MCLK Frequency, Normal Operation, Converting AD7734 ...
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... The AD7734 noise will not vary significantly with MCLK frequency. Chopping Enabled The first mode, in which the AD7734 is configured with chopping enabled (CHOP = 1), provides very low noise with lower output rates. Table 4 to Table 6 show the –3 dB Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled ...
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... Chopping Disabled The second mode, in which the AD7734 is configured with chopping disabled (CHOP = 0), provides faster conversion time while still maintaining high resolution. Table 7 to Table 9 show the –3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively ...
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... MCLK OUT is capable of driving one CMOS load. Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7734 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus ...
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... Serial data input (Schmitt triggered) with serial data being written to the input shift register on the part. Data from this input shift register is transferred to any AD7734 register, depending on the address bits of the communications register Digital Supply Voltage Nominal. ...
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... AD7734 REGISTER DESCRIPTION Table 11. Register Summary Register Addr (hex) Communications 00 I/O Port 01 Revision 02 Test 03 ADC Status 04 Checksum 05 ADC Zero-Scale Calibration 06 ADC Full-Scale 07 1 Channel Data 08–0B 1 Channel Zero-Scale Cal. 10–13 1 Channel Full-Scale Cal. 18–1B 1 Channel Status 20–23 1 Channel Setup 28–2B 1 Channel Conversion Time 30– ...
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... Register Access The AD7734 is configurable through a series of registers. Some of them configure and control general AD7734 features, while others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the communications register, i.e., any communication to the AD7734 must start with a write to the communications register specifying which register will be subsequently read or written ...
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... RDYFN This bit is used to control the function of the RDY pin on the AD7734. When this bit is reset to 0, the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will only go low if all enabled channels have unread data. ...
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... Default 0 Checksum Register 16 Bits, Read/Write Register, Address 05h This register is described in the Using the AD7734/AD7734/AD7738 Checksum Register application note (www.analog.com/UploadedFiles/Application_Notes/71751876 AN626_0.pdf). ADC Zero-Scale Calibration Register 24 Bits, Read/Write Register, Address 06h, Default Value 800000h The register holds the ADC zero-scale calibration coefficient. ...
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... Bits, Read-Only Register, Address 20h–23h, Default Value 20h × Channel Number These registers contain individual channel status information and some general AD7734 status information. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for more details) ...
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... Conversion Time (µs) = (FW × 207)/MCLK Frequency (MHz), the FW range 127. Bit 6 Bit 5 Bit Stat OPT Bit 6 Bit 5 Bit 4 FW (7-Bit Filter Word) Rev Page Bit 3 Bit 2 Bit 1 ENABLE 0 RNG1 Bit 3 Bit 2 Bit 1 11h AD7734 Bit 0 RNG0 0 Bit 0 ...
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... RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits. The AD7734 contains only one mode register. The two LSBs of the address are used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits ...
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... AD7734 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. ...
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... The AD7734 serial interface can be connected to the host device via the serial interface in several different ways. The CS pin can be used to select the AD7734 as one of several circuits connected to the host serial interface. When CS is high, the AD7734 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state ...
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... Reset The AD7734 can be reset by the RESET pin or by writing a reset sequence to the AD7734 serial interface. The reset sequence is N × × 1, which could be the data sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented interface. The AD7734 also features a power-on reset with a trip point and goes to the defined default state after power-on ...
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... After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7734 continues converting on the next enabled channel. The part will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels’ ...
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... Therefore the RDYFN bit in the I/O port register should be 0, and reading the result should always start before the next conversion is completed. The AD7734 will stay in continuous read mode as long as the DIN pin is low while the CS pin is low; therefore, write 0 to the AD7734 while reading in continuous read mode. To exit continuous read mode, take the DIN pin high for at least 100 ns after a read is complete ...
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... AD7734 CIRCUIT DESCRIPTION The AD7734 is a sigma-delta ADC that is intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, and PLC systems. It contains thin film resistor dividers, a multiplexer, an input buffer, a sigma-delta (or charge balancing) ADC, a digital filter, a clock oscillator, a digital I/O port, and a serial communications interface ...
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... Analog Input’s Extended Voltage Range The AD7734 output data code span corresponds to the nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. The sigma-delta modulator was designed to fully cover a ±11.6 V analog input voltage; outside this range, the performance might degrade more rapidly. The adjacent channels are not affected ± ...
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... Sigma-Delta ADC The AD7734 core consists of a charge balancing sigma-delta modulator and a digital filter. The architecture is optimized for fast, fully settled conversion. This allows for fast channel-to- channel switching while maintaining inherently excellent linearity, high resolution, and low noise ...
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... The AD7734 includes on-chip circuitry to detect if the part has a valid reference for conversions. If the voltage between the REFIN(+) and REFIN(–) pins goes below the NOREF trigger voltage (0.5 V typ.) and the AD7734 is performing a conversion, the NOREF bit in the channel status register is set. 10.0 Rev ...
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... I/O pin or to synchronize the AD7734 with other devices in the system. When the SYNC bit in the I/O port register is set and the SYNC pin is low, the AD7734 does not process any conversion put into single conversion mode, continuous conversion mode, or any calibration mode, the AD7734 waits until the SYNC pin goes high and then starts operation ...
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... TO +10V BIAS2 AIN3 BIAS3 BIASHI BIASLO AV DD +VIN VOUT +2.5V REFIN(+) AD780 REFIN(–) TEMP + + 10µF 0.01µF 10µF Figure 29. Typical Connections for the AD7734 Application R=15.5kΩ CLOCK GENERATOR 24-BIT MUX Σ-∆ ADC 7R BUFFER R R AD7734 ...
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... ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 18. Ordering Guide AD7734 Products Temperature Package AD7734BRU –40°C to +105°C © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies ...