AD9238 Analog Devices, AD9238 Datasheet

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AD9238

Manufacturer Part Number
AD9238
Description
Dual 12-Bit, 20/40/65 MSPS, 3 V ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD9238

Resolution (bits)
12bit
# Chan
2
Sample Rate
65MSPS
Interface
Par
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref) p-p,1 V p-p,2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP,QFP

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FEATURES
Integrated dual 12-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dB (to Nyquist, AD9238-65)
SFDR = 80.5 dBc (to Nyquist, AD9238-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
Battery-powered instruments
Hand-held scopemeters
Low cost, digital oscilloscopes
GENERAL DESCRIPTION
The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and-hold amplifiers (SHAs) and an
integrated voltage reference. The AD9238 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
WB-CDMA, CDMA2000, WiMAX
12-Bit, 20 MSPS/40 MSPS/65 MSPS
Fabricated on an advanced CMOS process, the AD9238 is available
in a Pb-free, space saving, 64-lead LQFP or LFCSP and is
specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 ©2003–2010 Analog Devices, Inc. All rights reserved.
REFB_B
REFB_A
REFT_B
REFT_A
VIN+_B
VIN–_B
VIN+_A
VIN–_A
SENSE
AGND
VREF
Pin-compatible with the AD9248, 14-bit 20MSPS/
40 MSPS/65 MSPS ADC.
Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to
suit an application.
Low power consumption: AD9238-65: 65 MSPS = 600 mW,
AD9238-40: 40 MSPS = 330 mW, and AD9238-20: 20 MSPS =
180 mW.
Typical channel isolation of 85 dB @ f
The clock duty cycle stabilizer (AD9238-20/AD9238-40/
AD9238-65) maintains performance over a wide range of
clock duty cycles.
Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
AD9238
FUNCTIONAL BLOCK DIAGRAM
SHA
SHA
0.5V
Dual A/D Converter
ADC
DRVDD DRGND
ADC
AVDD
Figure 1.
12
12
AGND
DUTY CYCLE
STABILIZER
BUFFERS
BUFFERS
CONTROL
OUTPUT
OUTPUT
CLOCK
MODE
MUX/
MUX/
IN
= 10 MHz.
12
12
www.analog.com
AD9238
MUX_SELECT
CLK_A
PWDN_A
OTR_A
CLK_B
DCS
SHARED_REF
PWDN_B
DFS
D11_B TO D0_B
D11_A TO D0_A
OEB_A
OTR_B
OEB_B

Related parts for AD9238

AD9238 Summary of contents

Page 1

... Battery-powered instruments Hand-held scopemeters Low cost, digital oscilloscopes GENERAL DESCRIPTION The AD9238 is a dual 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9238 uses a multistage differential pipelined architecture with output error correction ...

Page 2

... Changes to Terminology Section ................................................. 10 Changes to Figure 29 ...................................................................... 15 Changes to Clock Input and Considerations Section ................ 17 Changes to Figure 33 ...................................................................... 18 Changes to Data Format Section .................................................. 19 Added AD9238 LQFP Evaluation Board Section ...................... 21 Added Dual ADC LFCSP PCB Section ....................................... 34 Added Thermal Considerations Section ..................................... 44 Updated Outline Dimensions ....................................................... 45 Changes to Ordering Guide .......................................................... 46 Rev Page   ...

Page 3

... Changes to AC Specifications ......................................................... 4 Changes to Figure 1 .......................................................................... 4 Changes to Ordering Guide ............................................................ 5 Changes to TPCs 2, 3, and 6 ........................................................... 8 Changes to Clock Input and Considerations Section ................ 13 Added Text to Data Format Section ............................................ 15 Changes to Figure 9 ........................................................................ 16 Added Evaluation Board Diagrams Section ............................... 17 Update Outline Dimensions ......................................................... 24 2/03—Revision 0: Initial Version Rev Page AD9238 ...

Page 4

... IV 2.7 3.0 3.6 2.7 IV 2.25 3.0 3.6 2. ±0.01 V 180 VI 190 212 V 2.0 V ±0.1 V ±0.05 Rev Page AD9238BST/BCP-65 Typ Max Min Typ Max 12 12 ±0.50 ±1.1 ±0.50 ±1.1 ±0.50 ±2.4 ±0.50 ±2.5 ±0.35 ±0.35 ±0.35 ±0.8 ±0.35 ±1.0 ±0.60 ±0.70 ±0.50 ±1.4 ±0.55 ±1.75 ±4 ± ...

Page 5

... AD9238BST/BCP-40 AD9238BST/BCP-65 Min Typ Max Min Typ 70.4 70.3 70.1 69.7 70.3 69.3 68.7 70.0 68.3 67.6 70.2 70.1 69.9 69.4 70.1 68.9 68.1 69.1 67.9 66.6 11.5 11.4 11.4 11.3 11.4 11.2 11.1 11.3 11.1 10.9 −85.0 −80.0 86.0 86.0 85.0 76.7 86.0 80.0 72.5 80.5 75.0 −85.0 −85.0 AD9238 Max Unit Bits Bits Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB ...

Page 6

... Full OUT-OF-RANGE RECOVERY TIME Full 1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24). 2 Output delay is measured from clock 50% transition to data 50% transition, with load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. ...

Page 7

... V to DRVDD + 0.3 V ESD CAUTION −0 AVDD + 0.3 V −0 AVDD + 0.3 V −0 AVDD + 0.3 V −0 AVDD + 0.3 V −0 AVDD + 0.3 V −0 AVDD + 0.3 V −40°C to +85°C 150°C 300°C −65°C to +150°C = 54°C/W; 64-lead LFCSP, θ JA Rev Page AD9238 ...

Page 8

... DNC = DO NOT CONNECT Figure 3. 64-Lead LQFP Pin Configuration AGND 1 PIN 1 INDICATOR 2 3 AGND 4 AVDD AD9238 VREF 8 64-LEAD LFCSP 9 TOP VIEW 10 (Not to Scale) 11 AVDD 12 AGND AGND 16 NOTES 1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND. ...

Page 9

... SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A. EP For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND. Rev Page AD9238 ...

Page 10

... AD9238 TERMINOLOGY Aperture Delay SHA performance measured from the rising edge of the clock input to when the input signal is held for conversion. Aperture Jitter The variation in aperture delay for successive samples, which is manifested as noise on the input to the ADC. Integral Nonlinearity (INL) Deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ ...

Page 11

... MHz Figure 8. AD9238-65 Single-Tone SNR/SFDR vs. FS with MHz MHz Figure 9. AD9238-40 Single-Tone SNR/SFDR vs. FS with MHz 120 MHz Figure 10. AD9238-20 Single-Tone SNR/SFDR vs. FS with 126 MHz IN Rev Page 100 95 90 SFDR SNR 70 65 ...

Page 12

... Figure 11. AD9238-65 Single-Tone SNR/SFDR vs. AIN with f 100 90 80 SNR SFDR 70 SNR SNR –35 –30 –25 –20 –15 INPUT AMPLITUDE (dBFS) Figure 12. AD9238-40 Single-Tone SNR/SFDR vs. AIN with f 100 90 SNR SFDR 80 70 SNR SNR –35 –30 –25 –20 –15 INPUT AMPLITUDE (dBFS) Figure 13 ...

Page 13

... MHz Figure 21. Dual-Tone SNR/SFDR vs. AIN with f IN 100 – 201 MHz IN Rev Page AD9238 SNR SFDR SNR SNR –21 –18 –15 –12 –9 INPUT AMPLITUDE (dBFS MHz and SNR SFDR SNR SNR – ...

Page 14

... SAMPLE RATE (MSPS) Figure 26. Analog Power Consumption vs. FS 1.0 0.8 0.6 0.4 0 500 1000 1500 2000 2500 3000 CODE Figure 27. AD9238-65 Typical INL 1.0 0.8 0.6 0.4 0 500 1000 1500 2000 2500 3000 CODE Figure 28. AD9238-65 Typical DNL 60 3500 4000 3500 4000 ...

Page 15

... EQUIVALENT CIRCUITS AVDD VIN+_A, VIN–_A, VIN+_B, VIN–_B Figure 29. Equivalent Analog Input Circuit DRVDD Figure 30. Equivalent Digital Output Circuit AVDD CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF Figure 31. Equivalent Digital Input Circuit Rev Page AD9238 ...

Page 16

... ANALOG INPUT The analog input to the AD9238 is a differential, switched- capacitor, SHA that has been designed for optimum perfor- mance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance ...

Page 17

... Undersampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9238 important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9238 clock input ...

Page 18

... Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. Either channel of the AD9238 can be placed into standby mode independently by asserting the PDWN_A or PDWN_B pins recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption for the ADC ...

Page 19

... VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9238. The input range can be adjusted by varying the reference voltage applied to the AD9238, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly ...

Page 20

... REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum the internal reference of the AD9238 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading ...

Page 21

... MUX_SELECT pin. Refer to Table 8 for normal operating jumper positions. OUTPUTS The outputs of the AD9238 (and the data clock discussed earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to ensure the correct load on the outputs of the DUT, as well as the extra drive capability to the next part of the system. The 74VHC541s are latches, but on this evaluation board, they are wired and function as buffers ...

Page 22

... EVALUATION BOARD BAND-PASS CIRCUITRY FILTERS Figure 39. PCB Test Setup Rev Page JP2 JP3 JP4 JP5 In Out Out Out Out In Out Out Out Out Out In SINE SOURCE LOW JITTER (HP8644) AD9238 CLOCK CIRCUITRY OUTPUT INPUT AD9238 BUFFERS REFERENCE MODE SELECTION/EXTERNAL REFERENCE/CONTROL LOGIC ...

Page 23

... RV3299W 10 kΩ 0805 500 Ω 1206 10 kΩ 0805 22 Ω 1206 0 Ω RCA74204 22 Ω SMA200UP DIP06RCUP T1-1T TBLK06REM LOOPTP RED LOOPTP BLK LOOPMINI WHT LOOPMINI RED 64LQFP7X7 AD9238 SOL20 74VHC541 SOIC-8 AD822 SO8NC7 AD8138 TSSOP-14 74VHC04 ...

Page 24

... AD9238 LQFP EVALUATION BOARD SCHEMATICS Figure 40. Evaluation Board Schematic Rev Page ...

Page 25

... Figure 41. Evaluation Board Schematic (Continued) Rev Page AD9238 ...

Page 26

... AD9238 Figure 42. Evaluation Board Schematic (Continued) Rev Page ...

Page 27

... RP8 GND 2 RP8 18 3 RP8 RP8 22Ω R39 22Ω Rev Page AD9238 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω 22Ω ...

Page 28

... AD9238 LQFP PCB LAYERS Figure 44. PCB Top Side Silkscreen Rev Page ...

Page 29

... Figure 45. PCB Top Layer Rev Page AD9238 ...

Page 30

... AD9238 Figure 46. PCB Ground Plane Rev Page ...

Page 31

... Figure 47. PCB Split Power Plane Rev Page AD9238 ...

Page 32

... AD9238 Figure 48. PCB Bottom Layer Rev Page ...

Page 33

... Figure 49. PCB Bottom Silkscreen Rev Page AD9238 ...

Page 34

... AD9238 DUAL ADC LFCSP PCB The LFCSP PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with Analog Devices standard dual-channel data capture board (HSC-ADC- EVAL-DC), which together with ADI’s ADC Analyzer™ software allows for quick ADC evaluation ...

Page 35

... Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistor Resistor Pack Transformers AD9238 SN74LVCH16373A SN74LVC1G04 SN74VCX86 AD8139 Resistors Rev. C| Page AD9238 Package Value 0201 20 pF 0805 10 μF 0402 0.1 μF TAJD 10 μF 0201 0.1 μF Z5.531.3425.0 Wieland 25.602.5453.0 Wieland 0402 36 Ω ...

Page 36

... AD9238 LFCSP PCB SCHEMATICS ENCA D7A D7_A 49 D8A D8_A 50 D9A D9_A 51 DRVDD2 52 DRGND2 53 D10A D10_A 54 D11A D11_A 55 D12A D12_A 56 D13A D13_A 57 OTRA OTR_A 58 OEB_A 59 PDWN_A 60 MUX_SEL 61 SH_REF 62 CLK_A 63 VD AVDD5 64 EPAD 65 Figure 50. PCB Schematic ( Rev Page D7_B 32 D7B D6_B ...

Page 37

... Figure 51. PCB Schematic ( Rev Page AD9238 ...

Page 38

... AD9238 Figure 52. PCB Schematic ( Rev Page ...

Page 39

... LFCSP PCB LAYERS Figure 53. PCB Top-Side Silkscreen Rev Page AD9238 ...

Page 40

... AD9238 Figure 54. PCB Top-Side Copper Routing Rev Page ...

Page 41

... Figure 55. PCB Ground Layer Rev Page AD9238 ...

Page 42

... AD9238 Figure 56. PCB Split Power Plane Rev Page ...

Page 43

... Figure 57. PCB Bottom-Side Copper Routing Rev Page AD9238 ...

Page 44

... AD9238 THERMAL CONSIDERATIONS The AD9238 LFCSP has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature ...

Page 45

... Dimensions shown in millimeters Rev Page 9.20 9. 7.20 7.00 SQ TOP VIEW 6.80 (PINS DOWN 0.23 0.18 0.13 0.30 0.25 0.18 PIN 1 64 INDICATOR 1 * 4.85 EXPOSED PAD 4.70 SQ (BOTTOM VIEW) 4. 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD9238 ...

Page 46

... AD9238BSTRL-65 –40°C to +85°C AD9238BSTZ-65 –40°C to +85°C AD9238BSTZRL-65 –40°C to +85°C AD9238BCPZ-20 –40°C to +85°C AD9238BCPZRL-20 –40°C to +85°C AD9238BCPZ-40 –40°C to +85°C AD9238BCPZRL-40 –40°C to +85°C AD9238BCPZ-65 –40°C to +85°C AD9238BCPZRL-65 – ...

Page 47

... NOTES Rev Page AD9238 ...

Page 48

... AD9238 NOTES ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02640–0–11/10(C) Rev Page ...

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