AD9879 Analog Devices, AD9879 Datasheet
AD9879
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AD9879 Summary of contents
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... The 12-bit and 10-bit IF ADCs can convert direct IF inputs MHz and run at sample rates MSPS. A video input with an adjustable signal clamping level, along with the 10-bit ADC, allow the AD9879 to process an NTSC and a QAM channel simultaneously. The programmable Σ-Δ DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners ...
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... AD9879 TABLE OF CONTENTS Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 Thermal Characteristics .............................................................. 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 11 Transmit Path.............................................................................. 11 Data Assembler........................................................................... 11 Interpolation Filter ..................................................................... 12 Digital Upconverter.................................................................... 12 DPLL-A Clock Distribution...................................................... 12 Clock and Oscillator Circuitry ................................................. 12 Programmable Clock Output REFCLK................................... 13 Reset and Transmit Power-Down ............................................ 14 Σ ...
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... REVISION HISTORY 6/05—Rev Rev. A Updated Format.................................................................. Universal Changed OSCOUT to REFCLK....................................... Universal Changed REF CLK to REFCLK........................................ Universal Changes to Specifications Section................................................... 4 Changes to Figure 13 ...................................................................... 21 Changes to Equation 18.................................................................. 24 Changes to Equation 21.................................................................. 24 Changes to Outline Dimensions ................................................... 30 Changes to Ordering Guide........................................................... 30 8/02—Revision 0: Initial Version Rev Page AD9879 ...
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... AD9879 SPECIFICATIONS V = 3.3 V ± 5 3.3 V ± 10 4.02 kΩ, 75 Ω DAC load, unless otherwise noted. SET Table 1. Parameter OSCIN AND XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK Cycle to Cycle Jitter Tx DAC CHARACTERISTICS Resolution Maximum Sample Rate Full-Scale Output Current ...
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... III Full I Full II 60.0 Full II 9.67 Full II 60.3 Full II Full II 64.7 Full II 59.5 Full II 9.59 Full II 59.7 Full II Full II 63.8 Full II 43.9 Full II 7.0 Rev Page AD9879 Typ Max Unit 10 Bits MHz 4.5 ADC cycles 2.0 Vppd kΩ ±4 ±200 mV 59.9 dB 9.65 Bits 60 dB −73 − 59.0 dB 9.51 Bits 59.1 dB − ...
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... AD9879 Parameter Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation ( MHz) OUT Isolation Between Tx and IQ ADCs Isolation Between Tx and 10-Bit ADC Isolation Between Tx and 12-Bit ADC ADC-to-ADC (A = –0.5 dBFS MHz) ...
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... Rev Page Devices are 100% production tested at +25°C and guaranteed by design and characterization testing for commercial operating temperature range (−40ºC to +85°C). Parameter is guaranteed by design and/or characterization testing. Parameter is a typical value only. Test level definition is not applicable. AD9879 ...
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... DGND 26 TXSYNC TXIQ[5:0] 36 PROFILE 37 RESET PIN 1 AD9879 TOP VIEW (Pins Down) Figure 2. Pin Configuration Description Do Not Connect. Pins are not bonded to die. Pin Driver Digital Ground. Pin Driver Digital 3.3 V Supply. 12-Bit ADC Digital Output. Muxed I and Q ADCs Output. Sync Output, IF, I and Q ADCs. ...
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... ADC Analog Ground. 12-Bit ADC Analog 3.3 V Supply. 10-Bit ADC Decoupling Node. 10-Bit ADC Decoupling Node. Differential Input to 10-Bit ADC. 12-Bit ADC Decoupling Node. 12-Bit ADC Decoupling Node. Differential Input to IF ADC. Video Clamp Input, 12-Bit ADC. Rev Page AD9879 ...
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... AD9879 TERMINOLOGY Aperture Delay The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance. It specifies the time delay between the rising edge of the sampling clock input and when the input signal is held for conversion. Aperture Uncertainty (Jitter) Aperture jitter is the variation in aperture delay for successive samples ...
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... SNR when reduced output levels are required. DATA ASSEMBLER The AD9879 data path operates on two 12-bit words, the I and Q components, which compose a complex symbol. The data assembler builds the 24-bit complex symbols from four consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The nibbles are strobed synchronous to the master clock, MCLK, into the data assembler ...
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... The 12-bit and 10-bit IF ADCs can convert direct IF inputs MHz and run at sample rates MSPS. A video input with an adjustable signal clamping level along with the 10-bit ADC allow the AD9879 to process an NTSC and a QAM channel simultaneously. The programmable Σ-Δ DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners ...
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... Sampling the ADCs directly with the OSCIN clock requires (4) MCLK to be programmed to be twice the OSCIN frequency. (5) PROGRAMMABLE CLOCK OUTPUT REFCLK The AD9879 provides an auxiliary output clock on Pin 71, REFCLK. The value of the MCLK divider bit field, R, determines its output frequency as shown: f REFCLK ...
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... Power-Up Sequence On initial power-up, the RESET pin should be held low until the power supply is stable. Once RESET is deasserted, the AD9879 can be programmed over the serial port. The on-chip PLL requires a maximum of 1 millisecond after the rising edge of RESET or a change of the multiplier factor (M) to completely settle ...
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... OUTPUTS The AD9879 contains an on-chip Σ-Δ output that provides a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the programmed code, as shown in Figure 7. This bit stream can be low-pass filtered to generate a programmable dc voltage (Σ-Δ Code/4096)(V ...
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... AD9879 REGISTER MAP AND BIT DEFINITIONS 1 Table 4. Register Map Address (hex) Bit 7 Bit 6 0x00 SDIO SPI Bytes Bidirectional LSB First 0x01 PLL Lock Detect 0x02 Power- Power- Down PLL Down DAC Tx 0x03 Σ-∆ Output Control Word [3:0] 0x04 Flag 0 0x05 0 0 0x06 ...
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... OSCIN 0, f (PLL Derived) MCLK When using the AD9879 in systems where the Tx path and Rx path do not operate simultaneously, the value of M can be programmed from 1 to 31. The maximum f 236 MHz must be observed, whatever value is chosen for M. When M is set to 1, the internal PLL is disabled and all internal clocks are derived directly from OSCIN ...
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... REGISTER 0x0F—Tx PATH CONFIGURATION Bit 0: Single-Tone Tx Mode Active high configures the AD9879 for single-tone applications such as FSK. The AD9879 supplies a single frequency output as determined by the frequency tuning word selected by the active profile. In this mode, the TXIQ input data pins are ignored but should be tied to a valid logic voltage level ...
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... (fine)/2 + 6(coarse) − 14 8322 9879(0) where: fine is the decimal value of Bits [3:0]. coarse is the decimal value of Bits [7:8 level at AD9879 output in dBmV for fine = 0. 9879( level at output of AD8327 in dBmV. 8327 V is level at output of AD8322 in dBmV. 8322 Rev Page AD9879 ...
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... This functionality is controlled by the LSB-first bit in Register 0x00. The default is MSB first. When this bit is set active high, the AD9879 serial port is in LSB-first format. In LSB-first mode, the instruction byte and data bytes must be written from the LSB to the MSB. In LSB- first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle ...
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... When this bit is set default low, the AD9879 serial port is in MSB-first format. In MSB-first mode, the instruction byte and data bytes must be written from the MSB to the LSB. In MSB- first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. ...
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... The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9879. A look at the pass-band detail of the combined filter response (Figure 15 and Figure 16) indicates that to maintain an amplitude error of no more than 1 dB, signals are restricted to a bandwidth of no more than approximately 60 Rev ...
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... Figure 15. Cascaded Filter Pass-Band Detail ( keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of two prior to representing it to the AD9879. Without oversampling, the Nyquist bandwidth of the baseband data corresponds to the f ...
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... AD9879 is easiest to describe in terms (18) when an effect is first seen after an input value changes. Latency of I/Q data entering the data assembler (AD9879 input) to the DAC output is 119 f DC values applied to the data assembler input takes up to 176 f SYSCLK DAC output. (19) Frequency hopping is accomplished via changing the PROFILE input pin ...
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... For example Ω terminated input/output low-pass filter looks like a 25 Ω load to the AD9879. The output compliance voltage of the AD9879 is −0 +1 avoid signal distortion, any signal developed at the DAC output should not exceed +1.5 V. Furthermore, the signal may extend below ground as much as 0 ...
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... Power-Up and Hardware Reset—Upon initial power-up and every hardware reset, the AD9879 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9879 writes all 0s out of the 3-wire cable amplifier control interface. 2. ...
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... Figure 21. Rx Port Timing (Default Mode: Multiplexed IF ADC Data) REFCLK t MD MCLK RXIQ I[7:4] I[3:0] DATA RXSYNC IF DATA IF10 OR IF12 Figure 22. Rx Port Timing (Nonmultiplexed Data) 33Ω 33Ω Figure 23. Simple ADC Drive Configuration Rev Page AD9879 Q[7:4] Q[3:0] I[7:4] I[3:0] IF10 IF12 IF10 IF12 ...
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... V digital logic circuits, a DVDD section that is used to supply the digital supply pins of the AD9879, an AVDD section that is used to supply the analog supply pins of the AD9879, and a VANLG section that supplies the higher voltage analog components on the board. The 3 VDD section typically has the ...
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... MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low- pass filtering of the signals close to the MxFE further reduces the possibility of noise corrupting these signals. Rev Page AD9879 ...
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... AD9879 OUTLINE DIMENSIONS 2.90 2.70 2.50 0.50 0.25 VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9879BS −40°C to +85°C 1 AD9879BSZ −40°C to +85°C AD9879- Pb-free part. 23.20 BSC 20.00 BSC 3.40 1.03 MAX 18.85 REF 0.88 0. SEATING PLANE TOP VIEW (PINS DOWN) VIEW A PIN 1 0.23 100 1 0.11 7° ...
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... NOTES Rev Page AD9879 ...
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... AD9879 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02773-0-6/05(A) Rev Page ...