AD7724 Analog Devices, AD7724 Datasheet - Page 10

• Manufacturer Part Number: AD7724
• Description: Dual, 7th-Order, Sigma-Delta Modulator
• Manufacturer: Analog Devices

Specifications of AD7724

• Resolution (bits): 15bit
• # Chan: 2
• Sample Rate: 30MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 2.5V p-p,Uni 2.5V
• Adc Architecture: Sigma-Delta Modulator
• Pkg Type: QFP

AD7724
CIRCUIT DESCRIPTION
The AD7724 employs a sigma-delta conversion technique to
convert the analog input into a digital pulse train. The analog
input is continuously sampled by a switched capacitor modulator
at twice the rate of the clock input frequency (2 f
digital data that represents the analog input is in the ones’ den-
sity of the bit stream at the output of the sigma-delta modulator.
The modulator outputs the bit stream at a data rate equal to f
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to f
band of interest is reduced (Figure 5a). To reduce the quantiza-
tion noise further, a high order modulator is employed to shape
the noise spectrum, so that most of the noise energy is shifted
out of the band of interest (Figure 5b).
USING THE AD7724
ADC Differential Inputs
The AD7724 uses differential inputs to provide common-mode
noise rejection (i.e., the converted result will correspond to the
differential voltage between the two inputs). The absolute volt-
age on both inputs must lie between AGND and AVDD.
In the unipolar mode, the full scale-input range (VIN(+) –
VIN(–)) is 0 V to V
full-scale analog input range is ± V
allows complementary input signals. Alternatively, VIN(–) can
be connected to a dc bias voltage to allow a single-ended input
on VIN(+) equal to V
Differential Inputs
The analog input to the modulator is a switched capacitor design.
The analog input is converted into charge by highly linear sam-
pling capacitors. A simplified equivalent circuit diagram of the
analog input is shown in Figure 6. A signal source driving the
analog input must be able to provide the charge onto the sam-
pling capacitors every half MCLK cycle and settle to the required
accuracy within the next half cycle.
BAND OF INTEREST
BAND OF INTEREST
REF
MCLK
BIAS
. In the bipolar mode configuration, the
QUANTIZATION NOISE
/2, the noise energy contained in the
± V
NOISE SHAPING
REF
a.
b.
/2.
REF
/2. The bipolar mode
f
f
MCLK
MCLK
MCLK
/2
/2
). The
MCLK
.
Since the AD7724 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low differential mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role
in attaining the high performance available from the AD7724.
When a capacitive load is switched onto the output of an op
amp, the amplitude will momentarily drop. The op amp will try
to correct the situation and, in the process, hits its slew rate
limit. This nonlinear response, which can cause excessive ring-
ing, can lead to distortion. To remedy the situation, a low-pass
RC filter can be connected between the amplifier and the input
to the AD7724 as shown in Figure 7. The external capacitor at
each input aids in supplying the current spikes created during
the sampling process. The resistor in the diagram, as well as
creating a pole for the antialiasing, isolates the op amp from the
transient nature of the load.
The differential input impedance of the AD7724 switched capaci-
tor input varies as a function of the MCLK frequency, given by
the equation:
Even though the voltage on the input sampling capacitors may
not have enough time to settle to the accuracy indicated by the
resolution of the AD7724, as long as the sampling capacitor charg-
ing follows the exponential curve of RC circuits, only the gain
accuracy suffers if the input capacitor is switched away too early.
ANALOG
INPUT
VIN(+)
VIN(–)
Z
500
IN
500
MCLK
=
10
9
/
R
R
(
8
f
A
MCLK
A
A
B
B
B
C
C
)
A
k
Ω
GROUND
2pF
2pF
B
AC
VIN(+)
VIN(–)