AD7477 Analog Devices, AD7477 Datasheet
AD7477
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AD7477 Summary of contents
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... DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with these parts. The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is taken internally from V allows the widest dynamic input range to the ADC ...
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... Ordering Guide .......................................................................... 22 3/04—Rev Rev. D Added U.S. Patent Number .............................................................. 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section .............................................................................. 16 2/03—Rev Rev. C Changes to General Description ..................................................... 1 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 Changes to Ordering Guide ............................................................. 6 Changes to Typical Connection Diagram section ..................... 10 Changes to Figure 8 caption ...
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... V − 0.2 V − 0.2 V − 0 0.4 0.4 0.4 ±10 ±10 ± Straight (Natural) Binary Rev Page AD7476/AD7477/AD7478 = 2. 5. 1,2 Unit Test Conditions/Comments f = 100 kHz sine wave IN dB min B version 2 5. min T = 25° typ dB min B version 2 5. typ ...
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... AD7476/AD7477/AD7478 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation 7 Normal Mode (Operational) Full Power-Down 1 Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C. ...
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... AD7477 SPECIFICATIONS MHz SCLK Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 3 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution ...
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... AD7476/AD7477/AD7478 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode 5 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. 2 Operational from V = 2.0 V, with input high voltage, V ...
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... Rev Page AD7476/AD7477/AD7478 Unit Test Conditions/Comments f = 100 kHz sine wave SAMPLE dB min dB max dB max dB typ fa = 498.7 kHz 508.7 kHz dB typ fa = 498.7 kHz 508.7 kHz ns typ ps typ MHz typ @ 3 dB Bits LSB max ...
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... DD 2 Guaranteed by characterization. All input signals are specified with (10 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0 2.0 V. ...
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... maximum rating conditions for extended periods may affect −0 0 device reliability. 1 ±10 mA –40°C to +85°C −55°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 235 (0/+5)°C 255 (0/+5)°C 3.5 kV Rev Page AD7476/AD7477/AD7478 ...
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... SCLK input. The data stream from the AD7476 consists of four leading zeros followed by the 12 bits of conversion data; this is provided MSB first. The data stream from the AD7477 consists of four leading zeros followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first. The data stream from the AD7478 consists of four leading zeros followed by the eight bits of conversion data, followed by four trailing zeros, which is provided MSB first ...
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... FREQUENCY (kHz) Figure 6. AD7477 Dynamic Performance at 1 MSPS 8192 POINT FFT f = 1MSPS SAMPLE f = 100kHz IN SINAD = 71.67dB THD = –81.00dB SFDR = –81.63dB 350 400 450 500 8192 POINT FFT ...
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... AGND + 1 LSB). Gain Error For the AD7476/AD7477, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (such as V – 1.5 LSB) after the offset error has been adjusted out. For ...
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... The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, fast, micropower, single-supply ADCs. The parts can be operated from a 2. 5.25 V supply. When operated from either supply supply, the AD7476/AD7477/ AD7478 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock. ...
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... MSB of the 12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477 is followed by two trailing zeros. The 8-bit result from the AD7478 is followed by four trailing zeros. Alternatively, because the supply current required by the AD7476/AD7477/AD7478 is so low, a precision reference can be used as the supply source to the part ...
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... This mode is intended for fastest throughput rate performance. = 993 kSPS s Users do not have to worry about power-up times with the AD7476/AD7477/AD7478 remaining fully powered at all times. Figure 19 shows the general diagram of the AD7476/AD7477 2.35V DD AD7478 in normal mode. The conversion is initiated on the falling edge de- ...
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... SCLK. The device is fully powered up once 16 SCLKs have elapsed and, as shown in results from the next conversion. If the tenth falling edge of SCLK, the AD7476/AD7477/AD7478 again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low ...
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... SCLK falling edge and brought low again after a time initiate the conversion. QUIET When power supplies are first applied to the AD7476/AD7477/ AD7478, the ADC may power up in either power-down mode or normal mode. Allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. ...
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... Therefore, the first rising edge of SCLK after the CS falling edge provides the second leading zero. The 15th CS occurs before rising SCLK edge has DB0 provided or the final zero for the AD7477 and AD7478. This may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs. t ...
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... The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7476/ AD7477/AD7478. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without any glue logic required. In addition, the serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync) ...
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... SC2 1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 28. Interfacing to the DSP56xxx AD7476/AD7477/AD7478 to MC68HC16 Interface The serial peripheral interface (SPI) on the MC68HC16 is configured for master mode (MSTR = 1), the clock polarity bit (CPOL and the clock phase bit (CPHA The SPI is configured by writing to the SPI Control Register (SPCR). For more information on the MC68HC16, check with Motorola for the related documentation ...
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... OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 2.80 BSC 1.60 BSC PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.50 SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 30. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Rev Page AD7476/AD7477/AD7478 10° 0.60 4° 0.45 0° 0.30 ...
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... AD7476WARJZ-RL7 −40°C to +85°C 3 AD7477ARTZ-500RL7 −40°C to +85°C 3 AD7477ARTZ-REEL −40°C to +85°C 3 AD7477ARTZ-REEL7 −40°C to +85°C 3 AD7477SRTZ-REEL −55°C to +125°C 3 AD7478ARTZ-500RL7 −40°C to +85°C 3 AD7478ARTZ-REEL −40°C to +85°C 3 AD7478ARTZ-REEL7 −40°C to +85°C 3 AD7478SRTZ-REEL7 − ...
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... NOTES AD7476/AD7477/AD7478 Rev Page ...
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... AD7476/AD7477/AD7478 NOTES ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01024-0-1/09(F) Rev Page ...