AD7470 Analog Devices, AD7470 Datasheet - Page 12
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AD7470
Manufacturer Part Number
AD7470
Description
10-Bit, 2.7 V to 5.25 V, 1.75 MSPS Low Power ADC
Manufacturer
Analog Devices
Datasheet
1.AD7470.pdf
(20 pages)
Specifications of AD7470
Resolution (bits)
10bit
# Chan
1
Sample Rate
1.75MSPS
Interface
Par
Analog Input Type
SE-Uni
Ain Range
Uni (Vref)
Adc Architecture
SAR
Pkg Type
SOP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7470ARUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD7470/AD7472
PARALLEL INTERFACE
The parallel interfaces of the AD7470 and AD7472 are 10 bits
and 12 bits wide, respectively. The output data buffers are acti-
vated when both CS and RD are logic low. At this point, the con-
tents of the data register are placed onto the data bus. Figure 10
shows the timing diagram for the parallel port.
Figure 11 shows the timing diagram for the parallel port when
CS and RD are tied permanently low. In this setup, once BUSY
line goes from high to low, the conversion process is completed.
CONVST
CLK IN
BUSY
DB
CS
RD
X
t
2
CONVST*
CONVST*
t
CONVERT
BUSY
BUSY
DBx
DBx
CS
RD
*CONVST SHOULD GO HIGH WHEN THE CLK IS HIGH OR BEFORE THE FIRST CLK CYCLE.
*CONVST SHOULD GO HIGH WHEN THE CLK IS HIGH OR BEFORE THE FIRST CLK CYCLE.
Figure 11. Parallel Port Timing with CS and RD Tied Low
Figure 12. Wake-Up Timing Diagram (Burst Clock)
t
t
4
3
t
t
2
2
DATA N
t
6
t
5
t
t
Figure 10. Parallel Port Timing
CONVERT
CONVERT
t
7
t
8
–12–
t
4
t
3
The data is available on the output bus slightly before the falling
edge of BUSY.
It is important to point out that data bus cannot change state
while the ADC is doing a conversion as this would have a detri-
mental effect on the conversion in progress. The data out lines
will go three-state again when either the RD or the CS line goes
high. Thus the CS can be tied low permanently, leaving the RD
line to control conversion result access. Refer to V
for output voltage levels.
t
6
t
5
t
WAKEUP
t
t
9
t
9
7
DATA N + 1
t
10
t
8
DRIVE
section
REV. B