AD7729 Analog Devices, AD7729 Datasheet
AD7729
Specifications of AD7729
Available stocks
Related parts for AD7729
AD7729 Summary of contents
Page 1
... MODULATOR ADJUST FILTER DIVIDE BY 2 MUX REFERENCE One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 Dual Sigma-Delta ADC with Auxiliary DAC AD7729 AVDD1 AVDD2 AUXDAC IRxP IRxN QRxP QRxN REFCAP REFOUT World Wide Web Site: http://www.analog.com © Analog Devices, Inc., 1998 ...
Page 2
... AD7729–SPECIFICATIONS MHz; RxPOWER1 = 0; RxPOWER0 = 1; MCLKDIV = 0; T CLK Parameter AD7729A REFERENCE REFCAP Absolute Voltage, V 1.3 REFCAP REFCAP TC 50 REFOUT Absolute Voltage, V 1.3 REFOUT REFOUT TC 50 ADC CHANNEL SPECIFICATIONS Resolution 15 ADC Signal Range BIAS REFCAP V REFCAP Differential Signal Range V BIAS ...
Page 3
... OUT |I | < 100 A OUT A max A max See Table I MCLK ON Comments YES REFOUT Enabled, BSCLK = MCLK YES REFOUT Disabled, ASCLK = MCLK/48 NO REFOUT Disabled NO REFOUT Enabled YES MCLK Active Levels Equal and DVDD NO Digital Inputs Static and Equal DVDD AD7729 ...
Page 4
... AD7729 Table II. Receive Section Signal Ranges Baseband Section Signal Range V 1 REFCAP V 1.3 V 10% REFOUT ADC ADC Signal Range 2 V REFCAP V BIAS Differential Input (AVDD1 – V REFCAP Single-Ended Input V to (AVDD1 – V REFCAP Signal Range Differential V V BIAS REFCAP Single-Ended V V BIAS ...
Page 5
... Figure 6. Auxiliary Serial Port ASPORT Figure 7. Baseband Serial Port BSPORT –5– AD7729 MCLK Figure 4. ASCLK Figure 5. BSCLK ...
Page 6
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7729 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 7
... Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are determined by the value of DVDD2. Active Low Reset Signal. This input resets the entire AD7729 chip, resetting the control registers and clearing the digital filters. The logic input levels (V are determined by the value of DVDD2 ...
Page 8
... Gain Error This is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. In the AD7729, gain error is specified for the auxiliary section. Gain Matching Between Channels This is the gain matching between the IRx and QRx channel and is expressed in dBs ...
Page 9
... HIGH SPEED BUFFER MHz 13 19.5 Figure 10. Example Circuit for Single-Ended Input –9– AD7729 AD7729 4.7k IRxP I CHANNEL IRxN 4.7k 100pF 100pF 4.7k QRxP Q CHANNEL QRxN 4.7k 100pF 100pF REFOUT 0.1 F VOLTAGE REFCAP REFERENCE 0.1 F AD7729 IRxP I CHANNEL 100pF IRxN QRxP Q CHANNEL 100pF QRxN REFOUT REFCAP VOLTAGE 0.1 F REFERENCE 0.1 F ...
Page 10
... Use of Digital Filtering to Remove the Out- of-Band Quantization Noise Digital Filter The digital filters used in the AD7729 receive section carry out two important functions. Firstly, they remove the out-of-band quantization noise which is shaped by the analog modulator. Secondly, they are also designed to perform system level filter- ing, providing excellent rejection of the neighboring channels ...
Page 11
... Due to the low-pass nature of the receive filters, a settling time is associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence the AD7729 digital filters have a settling time of 44.7 s (288 Receive Offset Calibration Included in the digital filter is a means by which receive offsets may be calibrated out ...
Page 12
... RxREADY Figure 18. Receive Offset Adjust Auxiliary Control Functions The AD7729 also contains an auxiliary DAC that may be used for AGC. This 10-bit DAC consists of high impedance current sources, designed to operate at very low currents while main- taining its dc accuracy. The DAC is buffered by an output am- plifier and allows a load ...
Page 13
... MCLK has the same value as the external MCLK. When this bit equals 1, the external MCLK is divided by 2 within the AD7729 so that the device operates at half the exter- nal clock frequency. Selects AutoCal when set to 1 and UserCal when set to 0. ...
Page 14
... SDO pin of the SPORT at a word rate of 270 kHz for each of I and Q, after a delay (see Figure 16). The data format is I followed by Q. The AD7729 will output 16 bits of data, the 15-bit word, which is in twos comple- ment format, and a flag bit. This flag bit (LSB) distinguishes ...
Page 15
... The analog ground plane should be allowed SCLK to run under the AD7729 to avoid noise coupling. The power supply lines to the AD7729 should use as large a trace as pos- SDIFS sible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals like ...
Page 16
... AD7729 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Small Outline (SOIC) (R-28) 0.7125 (18.10) 0.6969 (17.70 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead Thin Shrink Small Outline (TSSOP) (RU-28) 0.386 (9.80) 0.378 (9.60 ...