AD7827 Analog Devices, AD7827 Datasheet - Page 10

• Manufacturer Part Number: AD7827
• Description: 3/5V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7827

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.0V,Uni 2.5V
• Adc Architecture: Pipelined
• Pkg Type: DIP,SOIC

AD7827
AD7827 SERIAL INTERFACE
In order to achieve a high throughput rate, the serial port of the
AD7827 has been optimized for high speed serial protocols.
Many high speed serial protocols use a continuous serial clock
to transfer data, e.g., the serial ports of many popular DSPs like
the TMS320C5x, ADSP-21xx and DSP560xx. The serial inter-
face of the AD7827 is optimized for communication with such
devices.
The serial interface of the AD7827 uses a three-wire interface to
communicate with a Master. The serial clock pin (SCLK) is a
logic input and determines the bit transfer rate. The Receive
Frame Synchronization pin (RFS) is a logic output and used to
CONVST
SCLK
D
RFS
OUT
t
1
t
2
1
DB7
t
t
3
5
2
DB6
Figure 15. Serial Timing
3
DB5
t
6
–10–
t
DB4
4
7
synchronize the data with a continuous serial clock. The data
output pin (D
out onto this pin on the rising edge of the serial clock. The first
rising edge of the serial clock after the end of a conversion causes
the RFS pin to go logic low. (See Figure 15 below.) The D
leaves its high impedance state and the first MSB is shifted out
on the first SCLK rising edge after the end of conversion. The
remaining seven data bits are shifted out on subsequent SCLK
rising edges. The D
on the falling edge of the eighth SCLK after RFS goes low. The
RFS output goes high again on the rising edge of the ninth SCLK.
If the AD7827 does not receive a ninth SCLK, the RFS will be
reset logic high by the next falling edge of CONVST.
t
8
DB3
5
OUT
DB2
6
) is a logic output and serial data is shifted
OUT
pin enters its high impedance state again
DB1
7
DB0
8
t
t
9
4
t
11
t
10
OUT
REV. 0
pin