AD7721 Analog Devices, AD7721 Datasheet
AD7721
Specifications of AD7721
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AD7721 Summary of contents
Page 1
... Settling time for a step input is 97.07 s while the group delay for the filter is 48.53 s when the master clock equals 15 MHz. The AD7721 can be operated with input bandwidths up to 229.2 kHz. The corresponding output word rate is 468.75 kHz. The part can be operated with lower clock frequencies also. ...
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... AD7721–SPECIFICATIONS Parameter SERIAL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR 2 Offset Error Unipolar Mode Bipolar Mode 2, 3 Full-Scale Error Unipolar Mode Bipolar Mode Unipolar Offset Drift Bipolar Offset Drift ANALOG INPUTS Signal Input Span (VIN1– ...
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... For Specified Operation V min CLK Uses CMOS Logic V max V min V max A max pF max V min |I | 200 A OUT V max |I | 1.6 mA OUT V min/V max V min/V max mA max Digital Inputs Equal max Active Mode W max Standby Mode AD7721 DD ...
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... All digital outputs are timed with the load circuit below and, except for t 3 The AD7721 is production tested with MHz for parallel mode operation and at 15 MHz for serial mode operation. However guaranteed by character- CLK ization to operate with CLK frequencies down to 100 kHz. ...
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... AD7721 WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATION SCLK/DB7 1 DB6 28 DB8 DB9 RFS/DB10 DVAL/SYNC SDATA/DB11 AGND 5 24 AD7721 DGND 6 23 VIN2 TOP VIEW (Not to Scale) DSUBST 7 22 VIN1 DGND 8 REFIN 21 STBY/DB0 9 20 AGND CAL/DB1 ...
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... MHz MHz (CLK = 15 MHz). Serial Mode Only CS, RD select the serial interface mode of operation, the AD7721 must be powered up with CS, RD and WR all tied to DGND. After two clock cycles, the AD7721 switches into serial mode. These pins must remain low during serial operation. ...
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... RD high, these pins are high impedance. Control functions such as CAL, UNI and STBY, which are available as pins in serial mode, are available as bits in parallel mode. Table I lists the contents of the control register onboard the AD7721. This register is written to in parallel mode using the WR pin. Control ...
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... USING THE AD7721 ADC Differential Inputs The AD7721 uses differential inputs to provide common-mode noise rejection. In the bipolar mode configuration, the analog input range is midway between successive integer LSB values. The output code is 2s complement binary with 1 LSB = 0. paral- lel mode and serial mode ...
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... INPUT Figure 5. Simple RC Antialiasing Filter Figure 6 shows a simple circuit that can be used to drive the AD7721 in unipolar mode. The input of the AD7721 is sampled by a 1.6 pF input capacitor. This creates glitches on the input of the modulator. By placing the RC filter directly before the AD7721, rather than before the operational amplifier, these ...
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... CLK reducing the clock frequency to 5 MHz leads to a sample fre- quency of 10 MHz, an output word rate of 156.25 kHz and a corner frequency of 76.4 kHz. The AD7721 can be operated with clock frequencies down to 100 kHz. Power Supply Sequencing If separate analog and digital supplies are used, care must be taken to ensure that both supplies remain within 0 ...
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... The AD7721 employs 2 FIR filters in series. The first filter is a 128 tap filter that samples the output of the modulator at f The second filter tap half-band filter that samples the output of the first filter at f /16 and decimates by 2 ...
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... CS and RD should be tied to DGND permanently except when control information is being written to the AD7721. DRDY goes high for 2 clock cycles to indicate that new data is available from the interface. The AD7721 outputs this data after the falling edge of DRDY. This DRDY pin can be used to drive an edge-triggered interrupt of a microprocessor ...
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... DSP. This will cause the sampling rate, the output word rate and the bandwidth of the AD7721 to be reduced by a proportional amount. The ADSP-21xx family can operate with a maximum serial clock of 13.824 MHz, the DSP56002 uses a maximum serial clock of 13 ...
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... DSP to the AD7721. When a control word is being written to the AD7721, Bits and Bits 9 to 10, which are test bits, need to be loaded with zeros. Therefore, pull-down resistors are used so that Pins and are tied to ground when the control register is being loaded. DMA13– ...
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... Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed AD7721 to run under the AD7721 to avoid noise coupling. The power supply lines to the AD7721 should use as large a trace as pos- DRDY sible to provide low impedance paths and reduce the effects of WR glitches on the power supply line ...
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... AD7721 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.005 (0.13) MIN 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-28) 1.565 (39.70) 1.380 (35.10 0.580 (14.73) 0.485 (12.32 0.060 (1.52) PIN 1 0.015 (0.38) 0.150 (3.81) MIN 0.022 (0.558) 0.100 0.070 SEATING (2.54) (1.77) PLANE 0.014 (0.356) BSC ...