AD7715 Analog Devices, AD7715 Datasheet
AD7715
Specifications of AD7715
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AD7715 Summary of contents
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... The AD7715 features a differential analog input as well as a differential reference input. It operates from a single supply ( V). It can handle unipolar input signal ranges mV mV 1.25 V and 2 can also handle bipolar input signal ranges of ± ...
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... Digital Interface.......................................................................... 29 Configuring the AD7715............................................................... 31 Microcontroller/Microprocessor Interfacing ............................. 32 AD7715 to 68HC11 Interface ................................................... 32 AD7715 to 8XC51 Interface...................................................... 33 AD7715 to ADSP-2103/ADSP-2105 Interface ....................... 33 Code For Setting Up The AD7715............................................... 34 C Code for Interfacing AD7715 to 68HC11........................... 34 Applications Information .............................................................. 36 Pressure Measurement............................................................... 36 Temperature Measurement ....................................................... 37 Smart Transmitters..................................................................... 38 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 40 Rev Page ...
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... V 0 Rev Page AD7715 Conditions/Comments Guaranteed by design; filter notch ≤ Depends on filter cutoffs and selected gain Filter notch ≤ Typically ±0.0004% For gains of 1 and 2 For gains of 32 and 128 Specifications for AIN and REF IN unless noted At dc ...
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... AD7715 1 Parameter Min LOGIC OUTPUTS (Including MCLK OUT Output Low Voltage Output Low Voltage Output High Voltage 4 Output High Voltage DV OH Floating State Leakage Current 13 Floating State Output Capacitance Data Output Coding 1 Temperature range as follows: A version, −40°C to +85°C. ...
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... Rev Page AD7715 MIN Conditions/Comments Guaranteed by design; filter notch ≤ Depends on filter cutoffs and selected gain Filter notch ≤ Typically ±0.0004% For gains of 1 and 2 For gains of 32 and 128 Specifications for AIN and REF IN unless noted At dc ...
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... AD7715 1 Parameter Min LOGIC OUTPUTS (Including MCLK OUT Output Low Voltage Output High Voltage Floating State Leakage Current 13 Floating State Output Capacitance Data Output Coding 1 Temperature range as follows: A version, −40°C to +85° calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the temperature of interest ...
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... REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK MHz 2.4576 MHz, unless otherwise noted. All specifications T Table 3. Min Parameter SYSTEM CALIBRATION 1 Positive Full-Scale Calibration Limit 1 Negative Full-Scale Calibration Limit 2 Offset Calibration Limit 2 0.8 × ...
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... See Figure 8 and Figure 9. 3 CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7715 is production tested with ...
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... V DD −0 0 −0 0 −0 0 −40°C to +85°C −65°C to +150°C 150°C 450 mW 105°C/W 260°C 450 mW 75°C/W 260°C 450 mW 128°C/W +260°C 450 mW >4000 V Rev Page AD7715 ...
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... DRDY Logic Output. A logic low on this output indicates that a new output word is available from the AD7715 data register. The DRDY pin returns high upon completion of a read operation of a full output word data read has taken place between output updates, the DRDY line returns high for 500 × t DRDY is high, a read operation should not be attempted or in progress to avoid reading from the data register being updated ...
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... AD7715 can accept and still calibrate offset accurately. Full-Scale Calibration Range This is the range of voltages that the AD7715 can accept in the system calibration mode and still calibrate full scale correctly. Input Span In system calibration schemes, two voltages applied in sequence to the AD7715’ ...
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... AD7715 ON-CHIP REGISTERS The AD7715 contains four on-chip registers, which can be accessed by via the serial port on the part. The first of these is a communications register that decides whether the next operation is a read or write operation and also decides which register the read or write operation accesses. All communi- cations to the part must start with a write operation to the communications register ...
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... This is the default state of the interface, and on power-up or after a reset, the AD7715 is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost write operation to the device of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715 returns to this default state ...
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... Mode select bits. These bits select the operating mode of the AD7715 (see Table 13). CLK The clock bit (CLK) should be set in accordance with the operating frequency of the AD7715. If the device has a master clock frequency of 2.4576 MHz, then this bit should be set the device has a master clock frequency of 1 MHz, then this bit should be set ...
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... The data register on the part is a read-only 16-bit register that contains the most up-to-date conversion result from the AD7715. If the communications register data sets up the part for a write operation to this register, a write operation must actually take place to return the part to where it is expecting a write operation to the communications register (the default state of the interface) ...
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... MHz 1 MHz 250 Hz 100 Hz 500 Hz 200 Hz Table 17. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode) Filter First Notch and Output Data Rate MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 250 Hz ...
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... MHz 1 MHz 250 Hz 100 Hz 500 Hz 200 Hz Table 21. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode) Filter First Notch and Output Data Rate MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 250 Hz ...
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... AD7715 CALIBRATION SEQUENCES The AD7715 contains a number of calibration options as outlined in Table 13. Table 23 summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor when DRDY returns low at the end of the sequence ...
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... CIRCUIT DESCRIPTION The AD7715 is a Σ-Δ ADC with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. It contains a Σ-Δ (or charge-balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter, and a bidirectional serial commu- nications port. The part consumes only 450 μ ...
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... V 2.36 kΩ 670 Ω AIN(+) input AIN(−) is 2.5 V and the 526 Ω 150 Ω AD7715 is configured for bipolar mode with a gain of 2 and a 526 Ω 150 Ω 2.5 V, the analog input range on the AIN(+) input is REF 1. 3.75 V (that is, 2.5 V ± ...
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... The nominal reference voltage, V (REF IN(+) − REF IN(−)), REF for specified operation is 2.5 V for the AD7715-5 and 1.25 V for the AD7715-3. The part is functional with but with degraded performance as the output noise will, in terms of LSB size, be larger. REF IN(+) must always be greater than REF IN(− ...
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... AD7715. For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7715 at the 100 Hz rate giving a −3 dB bandwidth of 26.2 Hz. Post-filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz ...
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... This significantly limits the amount of passive antialiasing filtering which can be provided in front of the AD7715 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances simply result in a small dc offset error (a 10 kΩ ...
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... V /GAIN. However, the span (which is the difference REF between the bottom of the AD7715’s input range and the top of its input range) must take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommodated depends on whether the unipolar or bipolar mode is being used ...
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... REF which the system calibration can handle is ±0.85 × V Power-Up and Calibration On power-up, the AD7715 performs an internal reset that sets /GAIN to +0.25 × REF the contents of the internal registers to a known state. There are default values loaded to all registers after a power-on or reset. ...
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... The maximum recommended load on this pin is one CMOS load. When using a crystal or ceramic resonator to generate the clock of the AD7715, it may be desirable to then use this clock as the clock source for the system. In this case recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit ...
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... V supplies and 90 μA with 3.3 V supplies. This is because the on-chip oscillator circuit continues to run when the part is in its standby mode. This is important in applications where the system clock is provided by the clock of the AD7715, so that the AD7715 produces an uninterrupted master clock even when its standby mode. ...
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... However, because the resolution of the AD7715 is so high and the noise levels from the AD7715 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7715 should be designed such that the analog and digital sections are separated and confined to certain areas of the board ...
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... DIN or DOUT) take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the data register of the AD7715. DRDY goes low when a new data word is available in the output register reset high when a read operation from the data register is complete ...
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... Figure 8 is for a on the part. It can also be reset by writing a series the DIN input Logic 1 is written to the AD7715 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in three-wire systems that if the interface gets lost either via a software error or by some glitch in the system, it can be reset back into a known state ...
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... YES POLL DRDY BIT OF COMMUNICATIONS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN AND SETTING UP NEXT OPERATION READ FROM THE DATA REGISTER (38 HEX) Figure 10. Flow Chart for Setting Up and Reading from the AD7715 Rev Page READ FROM COMMUNICATIONS REGISTER NO DRDY ...
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... The rise and fall times of the digital inputs to the AD7715 (especially the SCLK input) should be no longer than 1 μs. Most of the registers on the AD7715 are 8-bit registers. This facilitates easy interfacing to the 8-bit serial ports of micro- controllers ...
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... ADSP-2103/ADSP-2105 are configured as active low outputs, and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7715 is active when either the RFS or TFS outputs from the ADSP- 2103/ADSP-2105 are active. The serial clock rate on the ADSP- 2103/ADSP-2105 should be limited to 3 MHz to ensure correct operation with the AD7715 ...
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... DRDY output is polled to determine if a new valid word is available in the data register. C CODE FOR INTERFACING AD7715 TO 68HC11 /* This program has read and write routines for the 68HC11 to interface to the AD7715 and the sample program sets the various registers and then reads 1000 samples from the part. */ #include <math.h> ...
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... PORTC & 0xfb ; /* /CS is low */ for(b=0;b<reglength;b++) { SPDR = 0; while(!(SPSR & 0x80)); /* wait until port ready before reading */ *datapointer++=SPDR; /* read SPDR into store array via datapointer */ } PORTC|=4; /* /CS is high */ } Rev Page AD7715 ...
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... AD7715 is significantly better than that of the integrating ADCs. The on-chip PGA allows the AD7715 to handle an analog input voltage range as low full-scale with V differential inputs of the part allow this analog input range to have an absolute value anywhere between AGND and AV when the part is operated in unbuffered mode ...
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... R L2 lead resistances present a small source impedance so it would not generally be necessary to turn on the buffer on the AD7715. If the buffer is required, the common-mode voltage should be set accordingly by inserting a small resistance between the bottom end of the RTD and AGND of the AD7715. In the application shown in Figure 16, an external 400 μ ...
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... OUT AGND DGND ISOLATED GROUND The AD7715 consumes only 450 μA, leaving 3 mA available for the rest of the transmitter. Figure 17 shows a block diagram of a smart transmitter which includes the AD7715. Not shown in Figure 17 is the isolated power source required to power the front end ...
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... PLANE 0.31 (0.0122) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA Figure 19. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev Page 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 45° 1.27 (0.0500) 0.40 (0.0157) AD7715 ...
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... V AD7715ARU-5REEL 5 V AD7715ARU-5REEL7 AD7715ARUZ AD7715ARUZ-5REEL7 5 V AD7715ACHIPS AD7715AN AD7715ANZ AD7715AR AD7715AR-3REEL AD7715ARZ AD7715ARZ-3REEL 3 V AD7715ARU AD7715ARU-3REEL 3 V AD7715ARU-3REEL7 AD7715ARUZ AD7715ARUZ-3REEL7 3 V AD7715ACHIPS EVAL-AD7715-3EBZ RoHS Compliant Part. ...