AD7710 Analog Devices, AD7710 Datasheet
AD7710
Specifications of AD7710
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AD7710 Summary of contents
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... AGND The AD7710 allows the user to read and write the on-chip calibration registers. This means that the microcontroller has pin negative, the part SS much greater control over the calibration procedure. ...
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... AD7710–SPECIFICATIONS REF IN(–) = AGND; MCLK MHz unless otherwise noted. All specifications T Parameter STATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity @ + MIN MAX 2, 3 Positive Full-Scale Error 5 Full-Scale Drift 2 Unipolar Offset Error 5 Unipolar Offset Drift 2 Bipolar Zero Error ...
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... Load Regulation Output Compliance SYSTEM CALIBRATION l4 Positive Full-Scale Calibration Limit l4 Negative Full-Scale Calibration Limit 15 Offset Calibration Limits 15 Input Span NOTES 12 The AD7710 is tested with the following V voltages. With AV BIAS and V = – BIAS 13 Guaranteed by design, not production tested. 14 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7710 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... The AD7710 is specified with a 10 MHz clock for AV than 10 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7710 is not in STANDBY mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5 ...
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... Data Valid to SCLK Hold Time PIN CONFIGURATION DIP AND SOIC SCLK 1 24 DGND MCLK MCLK OUT 3 22 SDATA DRDY AD7710 SYNC 5 20 RFS TFS MODE 6 19 TOP VIEW AIN1(+) 7 18 AGND (Not to Scale) I AIN1(– OUT AIN2(+) ...
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... Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. SYNC 5 Logic Input. Allows for synchronization of the digital filters when using a number of AD7710s. It resets the nodes of the digital filter. 6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode ...
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... AD7710 can accept and still calibrate offset accurately. Full-Scale Calibration Range This is the range of voltages that the AD7710 can accept in the system calibration mode and still calibrate full scale correctly. Input Span In system calibration schemes, two voltages applied in sequence to the AD7710’ ...
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... Activate Background Calibration. This activates background calibration on the channel selected by CH. If the background calibration mode is on, then the AD7710 provides continuous self-calibration of the reference and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. The major advantage of using this mode is that the user does not have to recalibrate the device when there is a change in the ambient temperature ...
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... FS11 and is in the range 19 to 2,000. With the nominal MHz, this results in a first notch frequency range from 9. 1.028 kHz. To ensure correct operation of the AD7710, the value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device. ...
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... Gain of 2 Gain of 4 Gain of 8 Gain of 16 21.5 21 19.5 21 20 19.5 19 18.5 18.5 18 15.5 15 –11– AD7710 /GAIN, the input full scale). REF Gain of 32 Gain of 64 Gain of 128 0.25 0.25 0.25 0.41 0.38 0.38 0.43 0.4 0.4 0.46 0.46 0.46 0.62 0.6 0.56 0.9 0.65 0.65 4 2.7 1 120 70 40 Gain of 32 Gain of 64 Gain of 128 19.5 18.5 17.5 18.5 17 ...
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... Figure 2b. Output Noise vs. Gain and Notch Frequency (Gains 128) The basic connection diagram for the part is shown in Figure 3. This figure shows the AD7710 in the external clocking mode with both the AV log 5 V supply. Some applications have separate supplies for both AV ...
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... ADC or comparator yields an SNR of 7.78 dB. REV. G The AD7710 samples the input signal at a frequency of 39 kHz or greater (see Table III result, the quantization noise is spread over a much wider frequency than that of the band of interest. The noise in the band of interest is reduced still further ...
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... For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7710 at the 100 Hz rate, giving a –3 dB bandwidth of 26.2 Hz. Post filtering can be applied to this to reduce the bandwidth and output noise to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz ...
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... The dc input impedance for the AD7710 is over The input appears as a dynamic load that varies with the clock frequency and with the selected gain (see Figure 7). The input sample rate, as shown in Table III, determines the time allowed for the analog input capacitor charged ...
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... V of 2.5 V, the input voltage range on the REF AIN(+) input AIN(–) is 1.25 V and the AD7710 is configured for bipolar mode with a gain of 1 and 2.5 V, the analog input range on the AIN(+) REF input is –1. +3.75 V. ...
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... AD7710 are acceptable, and no cali- bration is performed after power-on, issuing a SYNC pulse to the AD7710 will reset the AD7710’s digital filter logic the SYNC line, with R, C time constant longer than the power-on time, will perform the SYNC function. ...
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... MD2, MD1, MD0 of the control register. When invoked, the background calibration mode reduces the output data rate of the AD7710 by a factor of 6 while the –3 dB bandwidth remains unchanged. The advantage is that the part is continually per- forming calibration and automatically updating its calibration coefficients ...
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... A serial read to the AD7710 can access data from the output register, the control register, or from the calibration registers. A serial write to the AD7710 can write data to the control register or the calibration registers. Two different modes of operation are available, optimized for ...
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... SCLK output. With DRDY low, the RFS input is brought low. RFS going low enables the serial clock of the AD7710 and also places the MSB of the word on the serial data line. All subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock ...
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... The falling edge of TFS enables the internally generated SCLK output. The serial data to be loaded to the AD7710 must be valid on the rising edge of this SCLK signal. Data is clocked into the AD7710 on the rising edge of the SCLK signal with the MSB transferred first. On the last active high time of SCLK, the LSB is loaded to the AD7710 ...
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... Figures 12a and 12b show timing diagrams for reading from the AD7710 in external clocking mode. In Figure 12a, all the data is read from the AD7710 in one read operation. In Figure 12b, the data is read from the AD7710 over a number of read operations. Both read operations show a read from the AD7710’s output data register ...
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... SCLK signal. TFS should return high during the low time of SCLK. After TFS returns low again, the next bit of the data-word to be loaded to the AD7710 is clocked in on next high level of the SCLK input. On the last active high time of the SCLK input, the LSB is loaded to the AD7710 ...
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... In this case, the serial interface to the AD7710 in external clocking mode can be simplified by connecting the TFS line to the A0 input of the AD7710 (see Figure 14). This means that any write to the device will load data to the control register (because A0 is low while TFS is low), and any read to the de- vice will access data from the output data register or from the calibration registers (because A0 is high while RFS is low) ...
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... AD7710. The 8XC51 outputs the LSB first in a write operation, while the AD7710 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7710 outputs the MSB first during a read operation, while the 8XC51 expects the LSB first ...
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... MOSI and MISO lines. The 68HC11 is configured in master mode with its CPOL bit set to a Logic 0 and its CPHA bit set to a logic 1. With a 10-MHz master clock on the AD7710, the interface operates with all four serial clock rates of the 68HC11. DV ...
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... The on-chip PGA allows the AD7710 to handle an analog input voltage range as low full scale. The differential inputs of the part allow this analog input range to have an absolute ...
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... AD7710 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.005 (0.13) MIN 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1.185 (30.01) 0.295 (7.49) 1.165 (29.59) 0.285 (7.24) 1.145 (29.08) 0.275 (6.99 0.180 0.015 (0.38) MIN (4.57) MAX 0.100 0.022 (0.56) 0.060 (1.52) SEATING (2 ...
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... SEATING 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –29– AD7710 0.75 (0.0295) 45 0.25 (0.0098 1.27 (0.0500) 0.40 (0.0157) ...
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... AD7710 Revision History Location 3/04—Data Sheet changed from REV REV. G. Changes to SPECIFICATIONS Note Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Deleted AD7710 to ADSP-2105 Interface section Deleted Figure 19 and renumbered subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Changes to AD7710 to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 –30– Page REV. G ...
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