AD7712 Analog Devices, AD7712 Datasheet - Page 23

• Manufacturer Part Number: AD7712
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with 2 Analog Input Channels
• Manufacturer: Analog Devices

Specifications of AD7712

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip
• Ain Range: Bip (Vref) x 4,Bip (Vref)/(PGA Gain),Bip 10V,Bip 20V,Uni (Vref) x 4,Uni (Vref)/(PGA Gain),Uni 10V,Uni 20V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line, and the write operation does not have any
effect on the status of DRDY. A write operation to the control
register or the calibration register must always write 24 bits to
the respective register.
Figure 14a shows a write operation to the AD7712 with TFS
remaining low for the duration of the write operation. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7712
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7712 on the high level of this
REV. F
SDATA (I)
SDATA (I)
SCLK (I)
Figure 14b. External Clocking Mode, Control/Calibration Register Write Operation
( TFS Returns High During Write Operation)
Figure 14a. External Clocking Mode, Control/Calibration Register Write Operation
SCLK (I)
TFS (I)
TFS (I)
A0 (I)
A0 (I)
t
32
t
32
MSB
t
35
MSB
t
26
t
35
–23–
t
t
36
26
t
27
t
SCLK signal with the MSB transferred first. On the last active
high time of SCLK, the LSB is loaded to the AD7712.
Figure 14b shows a timing diagram for a write operation to the
AD7712 with TFS returning high during the write operation
and returning low again to write the rest of the data word. Tim-
ing parameters and functions are very similar to that outlined
for Figure 14a, but Figure 14b has a number of additional times
to show timing relationships when TFS returns high in the
middle of transferring a word.
Data to be loaded to the AD7712 must be valid prior to the
rising edge of the SCLK signal. TFS should return high during
the low time of SCLK. After TFS returns low again, the next bit
of the data-word to be loaded to the AD7712 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7712.
27
BIT N
t
36
t
30
t
35
BIT N+1
LSB
t
34
t
36
t
33
AD7712