AD7703 Analog Devices, AD7703 Datasheet
AD7703
Specifications of AD7703
Available stocks
Related parts for AD7703
AD7703 Summary of contents
Page 1
... Weigh Scales Portable Instrumentation Remote Data Acquisition GENERAL DESCRIPTION The AD7703 is a 20-bit ADC that uses a S-D conversion tech- nique. The analog input is continuously sampled by an analog modulator whose mean output duty cycle is proportional to the input signal. The modulator output is processed by an on-chip ...
Page 2
... AD7703–SPECIFICATIONS BP/ MODE = + Source Resistance = Parameter A/S Version STATIC PERFORMANCE Resolution 20 Integral Nonlinearity ±0.0015 MIN MAX 25°C ±0.003 ±0.003 MIN MAX Differential Nonlinearity ±0.5 MIN MAX 3 Positive Full-Scale Error ±4 ±16 4 Full-Scale Drift ± ...
Page 3
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 4
... See Figures CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7703 is production tested with f ...
Page 5
... LSB). calibrate offset. REF Full-Scale Calibration Range This is the range of voltages that the AD7703 can accept in the system calibration mode and still correctly calibrate full scale. Input Span In system calibration schemes, two voltages applied in sequence to the AD7703’s analog input define the analog input range. The ...
Page 6
... REF mode and the value of both positive and negative full scale in the Bipolar mode. SLEEP 11 Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10 µW power consumption. 12 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going ...
Page 7
... The AD7703 samples the input signal at 16 kHz, which spreads the quantization noise from 0 kHz to 8 kHz. Since the specified SDATA SERIAL DATA analog input bandwidth of the AD7703 is only Hz, the CLKIN noise energy in this bandwidth would be only 1/800 of the total CLKOUT ...
Page 8
... V) gives only a half-scale input to the AD7703 (1.25 V). This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by one bit (50%). ...
Page 9
... Specification CLKIN table under Dynamic Performance. Therefore, the first step in system design with the AD7703 is to select a master clock fre- quency suitable for the bandwidth and output data rate required by the application. ANALOG INPUT RANGES ...
Page 10
... System Gain 1 0 System Offset *DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other modes, DRDY falls as the device begins to settle. Calibration Mode Zero Scale Self-Calibration V AGND ...
Page 11
... The REF ), the offset voltage REF typical gain drift of the AD7703 is less than 40 LSB over the specified temperature range. Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry ...
Page 12
... AD7703 INPUT SIGNAL CONDITIONING Reference voltages from may be used with the AD7703, with little degradation in performance. Input ranges that cannot be accommodated by this range of reference voltages may be achieved by input signal conditioning. This may take the form of gain to accommodate a smaller signal range, or passive attenua- tion to reduce a larger input voltage range ...
Page 13
... V. Power supply sequenc- DD ing is, therefore, important. If separate analog and digital supplies are used, care must be taken to ensure that the analog supply is powered up first also important that power is applied to the AD7703 before signals the logic input pins in order to avoid REF IN any possibility of latch-up ...
Page 14
... Figure 15 shows the timing diagram for the SSC mode. Data is clocked out by an internally generated serial clock. The AD7703 divides each sampling interval into 16 distinct periods. Eight periods of 64 clock pulses are for analog settling and eight peri- ods of 64 clock pulses are for digital computation ...
Page 15
... SCLK. After the LSB has been transmitted, DRDY and SDATA go three-state low and the AD7703 is still transmitting data when a new data-word becomes available, the old data-word continues to be transmitted and the new data is lost. ...
Page 16
... AD7703 20-Lead Plastic Dual In-Line Package [PDIP] (N-20) Dimensions shown in inches and (millimeters) 0.985 (25.02) 0.965 (24.51) 0.295 (7.49) 0.945 (24.00) 0.285 (7.24) 0.275 (6.99 0.180 (4.57) 0.015 (0.38) MIN MAX 0.150 (3.81) 0.130 (3.30) SEATING 0.100 0.060 (1.52) 0.110 (2.79) 0.022 (0.56) PLANE (2.54) 0.050 (1.27) 0.018 (0.46) BSC 0.045 (1.14) 0.014 (0.36) COMPLIANT TO JEDEC STANDARDS MO-095-AE CONTROLLING DIMENSIONS ARE IN INCHES ...