AD5760 Analog Devices, AD5760 Datasheet
AD5760
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AD5760 Summary of contents
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... LSB accurate DAC 20-bit, 1 LSB accurate DAC 18-bit, 1 LSB accurate DAC 18-bit, 0.5 LSB INL 16-bit, 1 LSB accurate 5 V DAC ADR445 AD5780 product page ©2011-2012 Analog Devices, Inc. All rights reserved. AD5760 6.8kΩ 6.8kΩ INV V OUT 6kΩ AD5760 ADA4004-1 www.analog.com ...
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... DAC Architecture....................................................................... 20 Serial Interface ............................................................................ 20 Hardware Control Pins.............................................................. 21 On-Chip Registers...................................................................... 22 AD5760 Features ............................................................................ 25 Power- V......................................................................... 25 Configuring the AD5760 .......................................................... 25 DAC Output State ...................................................................... 25 Output Amplifier Configuration.............................................. 25 Applications Information .............................................................. 27 Typical Operating Circuit ......................................................... 27 Evaluation Board ........................................................................ 28 ...
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... REFN nV-sec REFP REFN nV-sec −10 V, see Figure 43 REFP REFN nV-sec see Figure 44 REFP REFN nV-sec see Figure 45 REFP REFN nV-sec On removal of output ground clamp nV-sec kΩ kΩ AD5760 ADA4898-1 ...
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... Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. 4 The AD5760 is configured in unity-gain mode with a low-pass RC filter on the output 300 Ω 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). ...
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... SCLK rising edge to SDO valid ( min SYNC rising edge to SCLK rising edge ignore 35 ns typ RESET pulse width low 150 ns typ RESET pulse activation time ) and timed from a voltage level Rev Page AD5760 = ...
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... AD5760 SCLK SYNC t 8 SDIN DB23 t 10 LDAC V OUT V OUT CLR V OUT RESET V OUT t 17 SCLK SYNC t 8 SDIN DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB0 t 15 ...
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... DB23 INPUT WORD FOR DAC N DB23 SDO DB0 DB23 INPUT WORD FOR DAC N – 1 DB0 DB23 INPUT WORD FOR DAC N UNDEFINED Figure 4. Daisy-Chain Mode Timing Diagram Rev Page AD5760 DB0 DB0 ...
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... AD5760 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents 100 mA do not cause SCR latch-up. Table 4. Parameter Rating V to AGND −0 + AGND − +0 −0 + DGND −0 ...
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... Ground Reference Pin for Analog Circuitry. V AGND OUT REFP V V AD5760 RESET REFN TOP VIEW V (Not to Scale) DGND DD CLR SYNC LDAC SCLK Figure 5. Pin Configuration AD5760 to its power-on status. should be decoupled to DGND. CC Rev Page AD5760 − 2.5 V can be connected to this pin. DD ...
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... A voltage in the range of −16 −2.5 V can be connected to SS must be decoupled to AGND. The paddle can be left electrically unconnected provided that a SS pins recommended that the paddle be thermally connected Rev Page Data Sheet AD5760 Features section for further details. AD5760 Features section for further details. ...
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... REFN V = +15V DD 0. –15V SS 0.10 0.05 0 AD8675 OUTPUT BUFFER T = 25° 10000 20000 30000 40000 50000 DAC CODE Figure 11. Differential Nonlinearity Error vs. DAC Code Span AD5760 60000 70000 V = +10V REFP V = –10V REFN V = +15V –15V SS 60000 70000 60000 70000 ...
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... AD5760 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 AD8675 OUTPUT BUFFER T = 25°C A –0.10 0 10000 20000 30000 40000 DAC CODE Figure 12. Differential Nonlinearity Error vs. DAC Code Span AD8675 OUTPUT BUFFER 0. 25°C A 0.07 0.05 0.03 0.01 –0.01 –0.03 –0.05 0 10000 20000 30000 40000 DAC CODE Figure 13. Differential Nonlinearity Error vs. DAC Code Span, × ...
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... REFP –0. –10V REFN AD8675 OUTPUT BUFFER 12.5 13.0 13.5 14.0 14.5 15.0 15.5 V /| Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0 25° REFP –0 REFN AD8675 OUTPUT BUFFER –0.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 V /| Figure 23. Midscale Error vs. Supply Voltage Span AD5760 14.5 15.5 16.5 16.0 16.5 14.5 15.5 16.5 ...
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... AD5760 0. 25° +10V REFP V = –10V 0.12 REFN AD8675 OUTPUT BUFFER 0.10 0.08 0.06 0.04 0.02 0 12.5 13. 0 13.5 14.0 14.5 15.0 V /| Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span 0 25° REFP 0.3 REFN AD8675 OUTPUT BUFFER 0.1 –0.1 –0.3 –0.5 –0.7 –0.9 7.5 8.5 9.5 10.5 11.5 12.5 V /| Figure 25. Full-Scale Error vs. Supply Voltage Span ...
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... AD8675 OUTPUT BUFFER 0.15 –40 – TEMPERATURE (°C) Figure 34. Full-Scale Error vs. Temperature 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0. +15V DD –0. –15V SS AD8675 OUTPUT BUFFER –0.30 –40 – TEMPERATURE (°C) Figure 35. Midscale Error vs. Temperature AD5760 9.0 9.5 10.0 80 100 ±10V SPAN +10V SPAN +5V SPAN 80 100 ...
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... AD5760 0.4 ±10V SPAN +10V SPAN +5V SPAN 0.2 0 –0.2 –0.4 –0 AD8675 OUTPUT BUFFER –0.8 –40 – TEMPERATURE (°C) Figure 36. Zero-Scale Error vs. Temperature 0 ±10V SPAN +10V SPAN –0.1 +5V SPAN –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0 –0 AD8675 OUTPUT BUFFER – ...
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... OUTPUT UNBUFFERED –15V AD8676 REFERENCE BUFFERS 600 +10V REFP V = –10V REFN 400 200 0 –200 –400 –600 TIME (Seconds) Figure 47. Voltage Output Noise, 0 Bandwidth AD5760 NEGATIVE POSITIVE REF ±10V REF 10V REF 5V REF ...
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... AD5760 100 100 FREQUENCY (Hz) Figure 48. Noise Spectral Density vs. Frequency 0. +15V –15V SS 0. +10V REFP V = –10V REFN 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 –0. 10k Figure 49. Glitch Impulse on Removal of Output Clamp Rev Page Data Sheet V = +15V –15V +10V REFP V = –10V REFN ...
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... For fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 kΩ output impedance of the AD5760, in which case the amplifier that determines the settling time. Digital-to-Analog Glitch Impulse ...
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... AGND through a ~6 kΩ internal resistor. OUT DAC ARCHITECTURE The architecture of the AD5760 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 50. The six MSBs of the 16-bit data-word are decoded to drive 63 switches E62. Each of these switches connects one of ...
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... In this mode, LDAC is held low while data is being clocked into the input shift register. The DAC output is updated on the rising edge of SYNC . Rev Page AD5760 AD5760* SDIN SCLK SYNC SDO SDIN AD5760* SCLK SYNC SDO SDIN AD5760* SCLK SYNC SDO ...
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... The AD5760 The AD5760 The DAC register is loaded with the clearcode register value, and the output is set accordingly The output is set according to the DAC register value The DAC register is loaded with the clearcode register value, and the output is set accordingly. ...
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... Clearcode register data 1 16 bits of data Rev Page DB5 DB4 DB3 DB2 SDODIS BIN/2sC DACTRI OPGND AD5760 Features section for further details. and R1 are connected in parallel, as shown in FB AD5760 DB3 DB2 DB1 AD5760 LSB DB1 DB0 ...
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... Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Reset Setting this bit to 1 returns the DB20 DB19 to DB3 0 Reserved AD5760 to its power-on state. Rev Page Data Sheet DB2 DB1 DB0 Software control register data ...
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... Output is clamped via ~6 kΩ to AGND. OUTPUT AMPLIFIER CONFIGURATION There are a number of different ways that an output amplifier can be connected to the AD5760, depending on the voltage references applied and the desired output voltage span. Unity-Gain Configuration Figure 52 shows an output amplifier configured for unity gain. ...
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... V. For this mode of operation, the RBUF bit of the control register must be cleared to Logic 0. V REFP 16-BIT DAC − REFN = REFN V REFN Figure 54. Output Amplifier in Gain of Two Configuration Rev Page Data Sheet 6.8kΩ 6.8kΩ 10pF FB INV V V OUT OUT AD8675 ADA4898-1 ADA4004-1 AD5760 ...
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... Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 55. Typical Operating Circuit Rev Page AD5760 09650-055 ...
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... EVALUATION BOARD Refer to the evaluation board available for the AD5790 to evaluate a 18-bit version or 20-bit version of the AD5760. An evaluation board is available for the AD5760 to aid designers in evaluating the high performance of the part with minimum effort. The evaluation kit includes a populated and tested AD5780 board interfaces to the USB port ...
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... LSB 24-Lead LFCSP_VQ ±2 LSB 24-Lead LFCSP_VQ Rev Page 2.75 2.65 2.50 PIN 1 INDICATOR (Chamfer 0.225 3.75 EXPOSED PAD 3.65 3. BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-24-5 CP-24-5 CP-24-5 CP-24-5 AD5760 ...
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... AD5760 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES Rev Page AD5760 ...
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... AD5760 NOTES ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09650-0-2/12(B) Rev Page Data Sheet ...