AD5735 Analog Devices, AD5735 Datasheet
AD5735
Specifications of AD5735
Related parts for AD5735
AD5735 Summary of contents
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... DAC CHANNEL C DAC CHANNEL D Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD5735 uses a versatile 3-wire serial interface that operates AD5737 ADR02 ADuM1411 ADP2303 AD5735 product page BOOST_x 7.4V TO 29.5V I OUT_x R SET_x CURRENT AND VOLTAGE OUTPUT RANGE ...
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... Reprogramming the Output Range ......................................... 31 Data Registers ............................................................................. 32 REVISION HISTORY 11/11—Rev Rev. A Added Comments to OUTPUT CHARACTERISTICS and ACCURACY, CURRENT OUTPUT Parameters in Table 1 ................................................................................................ 4 Changes to Power-On State of the AD5735 Section.................. 29 Changes to Readback Operation Section .................................... 37 7/11—Revision 0: Initial Version Control Registers........................................................................ 34 Readback Operation .................................................................. 37 ...
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... DAC CHANNEL C DAC CHANNEL D AD0 SW DYNAMIC 7.4V TO 29.5V V POWER CONTROL DAC 12 + DAC A INPUT REG A V OUT RANGE SCALING Figure 2. Rev Page AD5735 V A BOOST_A DC-TO-DC CONVERTER V SEN1 SEN2 OUT_A R1 R SET_A +V SENSE_A V OUT_A –V SENSE_A OUT_B OUT_C ...
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... AD5735 SPECIFICATIONS − BOOST_x SS GNDSW = 0 V; REFIN = 5 V; voltage outputs unless otherwise noted. Table 1. Parameter 1 VOLTAGE OUTPUT Output Voltage Ranges Resolution ACCURACY, VOLTAGE OUTPUT Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) ...
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... Rev Page AD5735 Test Conditions/Comments Assumes ideal resistor, see External Current Setting Resistor section for more information. Drift after 1000 hours 150°C J Guaranteed monotonic External R SET Drift after 1000 hours 150°C ...
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... AD5735 1 Parameter DC-TO-DC CONVERTER Switch Switch On Resistance Switch Leakage Current Peak Current Limit Oscillator Oscillator Frequency Maximum Duty Cycle 2 DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Pin Capacitance 2 DIGITAL OUTPUTS SDO, ALERT Pins Output Low Voltage ...
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... See Test Conditions/Comments ms 0.01 LSB p-p 0.5 nA/√Hz Rev Page AD5735 = 300 Ω; all specifications MIN MAX Test Conditions/Comments 5 V step to ±0.03% FSR range 10 V step to ±0.03% FSR range range range ...
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... AD5735 TIMING CHARACTERISTICS − BOOST_x SS GNDSW = 0 V; REFIN = 5 V; voltage outputs unless otherwise noted. Table Parameter Limit MIN MAX 198 ...
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... LSB Figure 3. Serial Interface Timing Diagram LSB MSB MSB Figure 4. Readback Timing Diagram Rev Page LSB NOP CONDITION LSB SELECTED REGISTER DATA t CLOCKED OUT 15 AD5735 ...
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... AD5735 LSB 1 2 SCLK SYNC DUT_ DUT_ X R/W SDIN AD1 AD0 SDO SDO DISABLED X X D15 D14 SDO_ STATUS STATUS ENAB Figure 5. Status Readback During Write, Timing Diagram 200µ (MIN OUTPUT OH PIN V (MAX 50pF 200µ Figure 6. Load Circuit for SDO Timing Diagrams Rev ...
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... Table 5. Thermal Resistance Package Type + 0 64-Lead LFCSP (CP-64- using BOOST_x ESD CAUTION using BOOST_x using BOOST_x )/θ Rev Page AD5735 ) is specified for a JEDEC JA θ Unit JA 20 °C/W ...
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... Only channels enabled to be cleared are cleared. For more information, see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to. PIN 1 1 SET_B 2 SET_A 3 4 AD0 5 AD1 6 AD5735 7 SCLK 8 TOP VIEW SDIN 9 (Not to Scale) SDO ...
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... Note that the addition OUT_B pin is added directly to the headroom requirement. OUT_B Supply Requirements—Slewing section. CC Rev Page AD5735 . This pin must stay within OUT_A . The difference in voltage OUT_A stage, OUT_A . This pin must stay within OUT_B ...
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... AD5735 Pin No. Mnemonic Description 45 AV Supply for DC-to-DC Circuitry. The voltage range is from 4 5 Supply for Channel C Current Output Stage (see Figure 71). This pin is also the supply for the V BOOST_C which is regulated the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77 ...
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... Figure 11. Integral Nonlinearity Error vs. Temperature AV = +15V –15V SS ALL RANGES MAX DNL 0 MIN DNL – TEMPERATURE (°C) +5V RANGE ±10V RANGE ±12V RANGE AV = +15V –15V SS OUTPUT UNLOADED 0 –40 – TEMPERATURE (°C) Figure 13. Total Unadjusted Error vs. Temperature AD5735 80 100 80 100 80 100 ...
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... AD5735 0.06 0.05 +5V RANGE 0.04 ±10V RANGE ±12V RANGE 0. +15V –15V SS 0.02 OUTPUT UNLOADED 0.01 0 –0.01 –40 – TEMPERATURE (°C) Figure 14. Full-Scale Error vs. Temperature 0.015 0.010 0.005 0 +5V RANGE ±10V RANGE –0.005 ±12V RANGE AV = +15V –0.010 –15V SS –0.015 OUTPUT UNLOADED – ...
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... A OUTPUT UNLOADED 4 0 –4 –8 – TIME (µs) Figure 24. Full-Scale Negative Step 15 0x7FFF TO 0x8000 0x8000 TO 0x7FFF +10V RANGE 25º –5 –10 –15 – TIME (µs) Figure 25. Digital-to-Analog Glitch AD5735 +15V = –15V 4 5 ...
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... AD5735 +15V –15V SS ±10V RANGE 25°C A OUTPUT UNLOADED 5 0 –5 –10 – TIME (s) Figure 26. Peak-to-Peak Noise (0 Bandwidth) 300 AV = +15V ±10V RANGE OUTPUT UNLOADED –15V T = 25° 200 100 0 –100 –200 – ...
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... TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL –40 – TEMPERATURE (°C) MAX DNL 0 MIN DNL AV = +15V –15V/0V SS ALL RANGES INTERNAL AND EXTERNAL R SET –40 – TEMPERATURE (°C) AD5735 80 100 SET = +15V = –15V/0V 80 100 SET 80 100 ...
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... AD5735 0.025 0.020 0.015 0.010 0.005 0 –0.005 AV = +15V –0.010 –15V SS –0.015 4mA TO 20mA RANGE, INTERNAL R –0.020 4mA TO 20mA RANGE, EXTERNAL R –0.025 –40 – TEMPERATURE (°C) Figure 37. Total Unadjusted Error vs. Temperature 0.020 0.015 0.010 0.005 0 – ...
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... TIME (ms) Figure 47. Output Current and V Settling Time BOOST_x with DC-to-DC Converter (See Figure 77 –40° +25° +105°C A 0mA TO 24mA RANGE 1kΩ LOAD 410kHz SW INDUCTOR = 10µH (XAL4040-103 0.25 0.50 0.75 1.00 1.25 1.50 TIME (ms) over Temperature (See Figure 77) AD5735 = 300Ω 1.75 ...
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... AD5735 0mA TO 24mA RANGE 1kΩ LOAD 410kHz SW INDUCTOR = 10µH (XAL4040-103 25° –0.25 0 0.25 0.50 0.75 1.00 TIME (ms) Figure 49. Output Current Settling Time with DC-to-DC Converter over AV (See Figure 77 20mA OUTPUT 10mA OUTPUT –2 –4 –6 – ...
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... TO 24mA RANGE 1kΩ LOAD EXTERNAL R SET 410kHz SW INDUCTOR = 10µH (XAL4040-103) 20 –40 – TEMPERATURE (°C) Figure 56. Output Efficiency vs. Temperature (See Figure 77) 0.6 0.5 0.4 0.3 0.2 0.1 0 –40 – TEMPERATURE (°C) Figure 57. Switch Resistance vs. Temperature AD5735 80 100 80 100 ...
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... Figure 61. REFOUT Voltage vs. Temperature (When the AD5735 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. ...
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... 14.4 14.2 14.0 13.8 13.6 13.4 13.2 13 /|AV |) Figure 68. Internal Oscillator Frequency vs 25° 0mA OUT Rev Page 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12 5.5V DD 12.6 –40 – TEMPERATURE (°C) Figure 67. Internal Oscillator Frequency vs. Temperature T = 25°C A 2.5 3.0 3.5 4.0 4.5 VOLTAGE (V) DD AD5735 80 100 5.0 5.5 Supply Voltage ...
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... Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the area of the glitch in nV-sec (see Figure 28 and Figure 45). Rev Page Data Sheet pin for which the output current is equal to the AD5735 is powered on specified as the ...
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... V BOOST_x to the channel’s dc-to-dc input. The V considered part of the dc-to-dc converter’s losses. × OUT BOOST _ x × Rev Page AD5735 quiescent current is considered is defined as the ratio of the power supply and the power delivered quiescent current is BOOST_x ...
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... I A1 OUT_x R SET Figure 71. Voltage-to-Current Conversion Circuitry , and connect −V directly to AGND. OUT_x SENSE_x must stay within ±3 AGND for specified opera- SENSE_x pin and the V LV_x can operate with either an external or internal SENSE_x and V OUT_x pin. OUT_x AD5735 ...
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... SCLK. Data is clocked in on the falling edge of SCLK. If packet error checking (PEC) is enabled, an additional eight bits must be written to the AD5735, creating a 32-bit serial interface (see the Packet Error Checking section). The DAC outputs can be updated in one of two ways: individual DAC updating or simultaneous updating of all DACs ...
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... AD5735 REGISTERS Table 8, Table 9, and Table 10 provide an overview of the registers for the AD5735. Table 8. Data Registers for the AD5735 Register Description DAC Data Registers The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel ...
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... DC_DC BIT AND THE INT_ENABLE BIT SET. STEP 3: WRITE VALUE TO THE DAC DATA REGISTER. STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2. SET THE OUTEN BIT TO ENABLE THE OUTPUT. Figure 74. Programming Sequence to Change the Output Range Rev Page AD5735 ...
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... Write to a control register DAC_AD0 DAC Channel 0 DAC A 1 DAC B 0 DAC C 1 DAC D D20 D19 D18 Rev Page Data Sheet D17 D16 DAC_AD1 DAC_AD0 AD5735 device is being D17 D16 D15 to D4 DAC_AD1 DAC_AD0 DAC data LSB D15 to D0 Data ...
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... OF12 to OF5 OF4 11111111 1 11111111 0 … … 00000000 0 … … 00000000 1 00000000 0 DAC_AD0 D15 to D4 DAC channel address Clear code AD5735 1111 1111 1111 1111 1111 1111 0000 OF3 to OF0 0000 0000 0000 0000 0000 0000 0000 ...
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... AD5735 CONTROL REGISTERS When writing to a control register, the format shown in Table 19 must be used. See Table 12 for information about the configura- tion of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Table 20) ...
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... voltage range (default voltage range 0 ±5 V voltage range 1 ±10 V voltage range current range current range current range Rev Page AD5735 RSET DC_DC OVRNG ...
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... Table 27 and Table 28. D13 D12 0 User program Description Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5735. If the watchdog timer feature is enabled, 0x195 must be written to the software register (Bits[D11:D0]) within the programmed timeout period (see Table 22). D12 ...
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... Read DAC D slew rate control register 0 0 Read status register 0 1 Read main control register 1 0 Read dc-to-dc control register Rev Page This second SPI transfer should be either a request AD5735 Device 1, Channel SR_CLOCK SR_STEP D17 D16 RD1 RD0 AD5735 LSB D15 ...
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... Denotes a PEC error on the last data-word received over the SPI interface. Ramp Active This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel). Over Temp This bit is set if the AD5735 V Fault This bit is set if a fault is detected on the V OUT_D ...
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... Rev Page DAC DAC DATA INPUT REGISTER REGISTER GAIN (M) REGISTER OFFSET (C) REGISTER Figure 75. Digital Offset and Gain Control + ( × + − DACRegiste can be configured to read back the contents of AD5735 is powered up, the status readback during a AD5735 DAC (1) 12 − 1 ...
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... V voltage reference with value. To improve the stability of the output current SET resistor, R1, can be bypassed SET pin of the AD5735. The external resistor is selected SET_x resistor and an external, 15 kΩ R SET resistor allows for improved SET resistor option. The external ...
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... The 24 mA through a 1 kΩ load. Rev Page Rate Output Change × × Size Update Clock Frequency LSB Size or in OUT_x . OUT_x AD5735 circuitry senses the output voltage and regulates AD5735 is capable of driving up to AD5735 provides ...
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... DC-DCx BIT = 1 29 410kHz 28 25°C A 28.8 28.7 DC-DCx BIT = 0 28.6 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) Figure 78. Operation on Reaching V AD5735 ramps up to the V MAX AD5735 contains a 0.425 Ω internal switch. The switch AD5735 dc-to-dc converter switching frequency can be supply of 4 Data Sheet , if still MAX 3.0 3.5 4.0 MAX value but MAX − ~0.4 V. ...
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... The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5735, a low ESR tantalum or ceramic capacitor of 10 μF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature ...
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... AD5735 Reducing AI Current Requirements CC Two main methods can be used to reduce the AI requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. These methods can be used together. Adding an External Compensation Resistor A compensation resistor can be placed at the COMP in series with the 10 nF compensation capacitor kΩ ...
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... APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT PINS ON THE SAME TERMINAL When using a channel of the AD5735, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. The two output pins can be tied together because only the voltage output or the current output can be enabled at any one time ...
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... A 0.01 μF capacitor between I ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5735. There is no maxi- mum capacitance limit for the current output of the AD5735. TRANSIENT VOLTAGE PROTECTION ...
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... ADuM1411. For ADuM1411 V SERIAL CLOCK IA ENCODE DECODE OUT V SERIAL DATA IB ENCODE DECODE OUT V IC SYNC OUT ENCODE DECODE V ID CONTROL OUT ENCODE DECODE Figure 85. 4-Channel Isolated Interface to the AD5735 AD5735 ) to SW DCDC x AD5735 SCLK SDIN SYNC LDAC ...
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... BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Resolution (Bits) AD5735ACPZ 12 AD5735ACPZ-REEL7 RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09961-0-11/11(A) 0.60 MAX 48 0.50 8.75 BSC BSC SQ 0.50 0. ...