AD573 Analog Devices, AD573 Datasheet
AD573
Available stocks
Related parts for AD573
AD573 Summary of contents
Page 1
... HIGH BYTE ENABLE (HBE) and LOW BYTE ENABLE (LBE) control the 8-bit and 2-bit three state output buffers. The AD573 is available in two versions for the +70 C temperature range, the AD573J and AD573K. The AD573S guarantees 1 LSB relative accuracy and no missing codes from – ...
Page 2
... Positive True Offset Binary 3.2 3.2 0.5 0.5 40 100 2.0 2.0 0 +4.5 5.0 +7.0 +4.5 –11.4 –15 –16.5 +11 potentiometer in place of the MAX –2– AD573K AD573S Typ Max Min Typ 10 10 1/2 1/2 2 1/2 1 +70 – 5.0 7.0 3.0 5.0 + –5 Positive True Binary Positive True Offset Binary 3 ...
Page 3
... D = Ceramic DIP Plastic DIP Plastic Leaded Chip Carrier. FUNCTIONAL DESCRIPTION A block diagram of the AD573 is shown in Figure 1. The posi- tive CONVERT pulse must be at least 500 ns wide. DR goes high within 1.5 s after the leading edge of the convert pulse indicating that the internal logic has been reset. The negative edge of the CONVERT pulse initiates the conversion ...
Page 4
... Figure 4a. Figure 4. Offset Trims Figure 5 shows the nominal transfer curve near zero for an AD573 in unipolar mode. The code transitions are at the edges of the nominal bit weights. In some applications it will be pref- erable to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics. ...
Page 5
... A SHA can also be used to accurately define the exact point in time at which the signal is sampled. For the AD573, a SHA can also serve as a high input impedance buffer. Figure 8 shows the AD573 connected to the AD582 monolithic SHA for high speed signal acquisition ...
Page 6
... AD573 can interface to a microprocessor system with little or no external logic. The most popular control signal configuration consists of de- coding the address assigned to the AD573, then gating this sig- nal with the system’s WR signal to generate the CONVERT pulse, and gating it with RD to enable the output buffers. The use of a memory address and memory WR and RD signals de- notes “ ...
Page 7
... CONVERT Pulse Generation The AD573 is tested with a CONVERT pulse width of 500 ns and will typically operate with a pulse as short as 300 ns. However, some microprocessors produce active WR pulses which are shorter than this. Either of the circuits shown in Fig- ure 13 can be used to generate an adequate CONVERT pulse for the AD573 ...
Page 8
... AD573 It is also possible to write a faster-executing assembly-language routine to control the AD573. Such a routine will require a de- lay between starting and reading the converter. This can be eas- ily implemented by calling the Apple’s WAIT subroutine (which resides at location $FCA8) after loading the accumulator with a number greater than or equal to two ...