AD5629R Analog Devices, AD5629R Datasheet - Page 10

• Manufacturer Part Number: AD5629R
• Manufacturer: Analog Devices

Specifications of AD5629R

• Resolution (bits): 12bit
• Dac Update Rate: 166kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5629R/AD5669R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
16-Lead
LFCSP
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
17
Pin No.
N/A
16-Lead
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
V
V
NOTES
1. EXPOSED PAD MUST BE TIED TO GND.
OUT
OUT
OUT
V
DD
Figure 3. 16-Lead LFCSP (CP-16-17)
A
C
E
1
2
3
4
AD5629R/AD5669R
(Not to Scale)
Exposed Pad (EPAD)
Mnemonic
LDAC
A0
V
V
V
V
V
V
CLR
V
V
V
V
GND
SDA
SCL
TOP VIEW
DD
OUT
OUT
OUT
OUT
REFIN
OUT
OUT
OUT
OUT
A
C
E
G
H
F
D
B
/V
REFOUT
12
11
10
9
GND
V
V
V
OUT
OUT
OUT
B
D
F
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can
be tied permanently low.
Address Input. Sets the least significant bit of the 7-bit slave address.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the supply
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
The AD5629R/AD5669R have a common pin for reference input and reference output.
When using the internal reference, this is the reference output pin. When using an external
reference, this is the reference input pin. The default for this pin is as a reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register are
updated with the data contained in the CLR code register—zero scale, midscale, or full
scale. The default setting clears the output to 0 V.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Parts.
Serial Data Input. This is used in conjunction with the SCL line to clock data into or out of
the 32-bit input shift register. It is a bidirectional, open-drain data line that should be
pulled to the supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of
the 32-bit input shift register.
The exposed pad must be tied to GND.
Rev. A | Page 10 of 28
V
REFIN
/V
Figure 4. 16-Lead TSSOP (RU-16)
REFOUT
V
V
V
V
LDAC
OUT
OUT
OUT
OUT
V
A0
DD
G
A
C
E
1
2
3
4
5
6
7
8
(Not to Scale)
AD5629R/
AD5669R
TOP VIEW
15
14
13
12
11
10
16
9
SCL
SDA
GND
V
V
V
V
CLR
OUT
OUT
OUT
OUT
B
D
F
H