AD9148 Analog Devices, AD9148 Datasheet
AD9148
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AD9148 Summary of contents
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... The current outputs are easily configured for various single-ended or differential circuit topologies. The LVDS data input interface includes FIFO to ease input timing ± IF POST DAC AQM PA ANALOG FILTER POST DAC AQM ©2010–2012 Analog Devices, Inc. All rights reserved. AD9148 www.analog.com ...
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... AD9148 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Input/Output Signal Specifications ............................................ 6 Digital Input Data Timing Specifications ................................. 7 AC Specifications .......................................................................... 8 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 Maximum Safe Power Dissipation ............................................. 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ...
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... Changes to Timing Optimization Section ................................... 48 Added Table 15 ................................................................................ 48 Changes to Filter Implementation Section .................................. 50 Changes to Figure 74 ...................................................................... 57 Deleted Test Access Port Section, Table 27, Figure 92, and Table 28 ............................................................................................. 68 Parameter, Table 2 ......... 6 Changes to Start-Up Sequence Section ........................................ 68 Deleted Figure 93 ............................................................................ 69 Deleted Table 29 .............................................................................. 70 6/10—Revision 0: Initial Version Rev Page AD9148 ...
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... AD9148 FUNCTIONAL BLOCK DIAGRAM 310MHz 310MHz –1 SINC MOD 1.2GHz DCIA_P/ DCIA_N FRAMEA_P/ FRAMEA_N 16 A[15:0]_P –1 SINC A[15:0]_N MOD –1 SINC 16 MOD B[15:0]_P/ B[15:0]_N FRAMEB_P/ FRAMEB_N DCIB_P/ DCIB_N –1 SINC MOD PROGRAMMING SERIAL REGISTERS IN/OUT PORT 310MHz/620MHz 500MHz/1GHz 500MHz/1GHz 2× ...
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... Power-Down Mode OPERATING RANGE 1 Based kΩ external resistor mA, maximum sample rate, unless OUTFS Min 8.66 −1.0 3.13 1.71 1.71 1.71 −1 FILTER BYPASSED, −1 Filter Enabled −40 Rev Page AD9148 Typ Max Unit 16 Bits ±2.1 LSB ±3.7 LSB ±0.001 % FSR ±2 % FSR 20.2 31. MΩ ...
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... AD9148 INPUT/OUTPUT SIGNAL SPECIFICATIONS AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CS, RESET, TMS, TDI, TCK) Input V Logic High (IOVDD = 1 ...
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... DAC1 32 AND 2× 2× 2× DAC2 DATAPATH CLK GENERATOR DACCLK AND DISTRIBUTOR DATAPATH 32 DAC3 2× AND 2× 2× DAC4 HB1 HB2 HB3 DAC AD9148 Unit Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles ms f DAC 1000 1000 ...
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... AD9148 AC SPECIFICATIONS AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 5. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR 400 MSPS MHz DAC OUT f = 600 MSPS 100 MHz DAC OUT f = 1000 MSPS 100 MHz DAC OUT TWO-TONE INTERMODULATION DISTORTION (IMD 400 MSPS, f ...
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... PCB vias 8-layer board, 25 PCB vias 10-layer board, 25 PCB vias 12-layer board, 25 PCB vias 4-layer board, 25 PCB vias 8-layer board, 25 PCB vias 10-layer board, 25 PCB vias 12-layer board, 25 PCB vias AD9148 is 125° available rate for a given DAC ...
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... AD9148 Table 8. Thermal Resistance and Maximum Power Package Type T (°C) PCB Layers A 196-ball CSP_BGA 85 12 196-ball CSP_BGA 85 12 196-ball BGA_ED 85 12 196-ball BGA_ED Heat sink is used in the thermal model × tall. Table 9. Power vs. f Rate and Functionality ...
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... POSITIVE AVDD33 AVSS CLK X TERMINAL Figure 4. Pin Configuration (Top View), Analog and Clock Domain Pins Rev Page IOUT3 IOUT3 A AUX3 AUX3 B AUX4 IOUT4 C IOUT4 AUX4 NEGATIVE CLK TERMINAL AD9148 ...
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... AD9148 SPI INTERFACE SDO CS G SDIO SCLK H J FrB DCIB K FrB DCIB IOVDD + Table 10. Pin Function Description Pin No. Mnemonic E6, E7, E8, E9 CVDD18 F5, F6, F7, F8, F9, F10 AVDD33 A1, A2, A5, A10, A13, A14, B1, ...
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... Recommended external bias circuit is shown in Figure 49. LVDS Data Input Pair, Port B (LSB). LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B LVDS Data Input Pair, Port B. Rev Page AD9148 ...
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... AD9148 Pin No. Mnemonic M7, L7 B6_P/B6_N M8, L8 B7_P/B7_N M9, L9 B8_P/B8_N M10, L10 B9_P/B9_N M11, L11 B10_P/B10_N K11, J11 B11_P/B11_N M12, L12 B12_P/B12_N K12, J12 B13_P/B13_N M13, L13 B14_P/B14_N M14, L14 B15_P/B15_N K2, J2 DCIB_P/DCIB_N K1, J1 FRAMEB_P/FRAMEB_N Description LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. ...
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... DATA DATA OUT –70 –75 –80 –85 – 100 150 200 250 300 350 f (MHz) OUT , 8× Interpolation, f OUT Digital Scale = 0 dBFS, Full-Scale Current = 20 mA AD9148 250 300 400 450 500 400 450 500 = 125 MSPS, DATA ...
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... AD9148 –30 –35 0dBFS, SECOND HARMONIC –6dBFS, SECOND HARMONIC –40 –12dBFS, SECOND HARMONIC –18dBFS, SECOND HARMONIC –45 –50 –55 –60 –65 –70 –75 –80 –85 – 100 150 f (MHz) OUT Figure 12. Second Harmonic vs. f OUT Full-Scale Current = 20 mA, 4× Interpolation, f – ...
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... PLL OFF PLL ON –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 0 50 100 150 200 f (MHz) OUT Figure 23. IMD vs PLL On and Off, OUT Digital Scale = 0 dBFS, Full-Scale Current = 20 mA AD9148 400 450 500 250 300 250 300 ...
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... AD9148 –144 –146 1×, 200MSPS 2×, 200MSPS –148 4×, 200MSPS 8×, 100MSPS –150 –152 –154 –156 –158 –160 –162 –164 –166 0 50 100 150 200 250 f (MHz) OUT Figure 24. Single-Tone NSD Performance vs. f 4× 200 MSPS, Full-Scale Current = 20 mA DATA –144 – ...
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... MHz, PLL On DATA START 1.0MHz STOP 368.6MHz #RES BW 30kHz VBW 30kHz SWEEP 1.685s (601 PTS) = 150 MHz, f OUT DAC 4× Interpolation, −3 dBFS AD9148 UPPER dBc dBm –77.98 –91.45 –82.65 –96.12 –82.28 –95.75 UPPER dBc dBm –73.79 –86.56 –82.99 –95.76 – ...
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... AD9148 CENTER 150.00MHz #RES BW 30kHz VBW 300kHz SWEEP 193.2ms (601 PTS) TOTAL CARRIER POWER –13.30dBm/15.3600MHz REF CARRIER POWER –19.14dBm/3.84000MHz RCC FILTER: ON FILTER ALPHA 0.22 FREQ LOWER OFFSET dBc INTEG BW 1 –19.14dBm 5.000MHz 3.840MHz –72.59 –91.81 10.00MHz 3.840MHz – ...
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... By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev Page (interpolation rate) and then filters out the DATA AD9148 ...
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... I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO). GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9148. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges ...
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... Figure 42. Serial Register Interface Timing LSB First SCLK t t PWH PWL t DCSB t DH INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 43. Timing Diagram for SPI Register Write t DV DATA BIT n DATA BIT n – 1 Figure 44. Timing Diagram for SPI Register Read AD9148 ...
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... AD9148 SPI REGISTER MAP Table 12. Register Map Register Addr Name Bit 7 Bit 6 0x00 Comm SDIO LSB/ direction MSB first 0x01 Power Power- Power- control Down DAC Down Set 1 DAC Set 2 0x03 Data format Binary Q first format enable 0x04 Interrupt Enable PLL ...
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... SED Status Rising Edge Samples[7:0] SED Status Rising Edge Samples[15:8] SED Status Falling Edge Samples[7:0] SED Status Falling Edge Samples[15:8] I Gain[7:0] Q Gain[7:0] Rev Page AD9148 Bit 2 Bit 1 Bit 0 Coeff_0i[2:0] Coeff_2i[4:0] Coeff_3i[6:3] Coeff_0q[2:0] Coeff_2q[4:0] Coeff_3q[6:3] Phase Word I[9:8] ...
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... AD9148 Register Addr Name Bit 7 Bit 6 0x54 FTW (LSB) 0x55 FTW 0x56 FTW 0x57 FTW (MSB) 0x58 Phase offset (MSB) 0x59 Phase offset (LSB) 0x5A DDS/mod Bypass control DDS/MOD 0x5C Die Temp Control 0 0x5D Die Temp 0 Control 1 0x5E Die temp LSB ...
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... Enables interrupt for FIFO Warning 2. Warning 2 Enable AED Enables interrupt for AED compare pass. compare pass Enable AED Enables interrupt for AED compare fail. compare fail Enable SED Enables interrupt for SED compare fail. compare fail Rev Page AD9148 Default ...
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... AD9148 Addr Register Name (Hex) Bit Event Flag 0 (All bits 06 7 are high when interrupt is active. Clear interrupt 6 by writing respective bit high Event Flag 1(All bits are 07 4 high when interrupt is active. Clear interrupt by writing respective 3 bit high). ...
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... Rising edge sync Rising edge of CLK samples sync input (1), falling edge of CLK samples sync input (0). Sync averaging Average sync input of number of samples. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. Rev Page AD9148 Default ). 11 PC_CLK 001 01 Read- only Read- only ...
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... AD9148 Addr Register Name (Hex) Bit Sync Control 1 11 5:0 Sync Status Data Receiver Control 14 6 Data Receiver Status FIFO Status Control Port 2:0 Name Function Sync phase request Offset of internal divided by 64 clock phase after sync. ...
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... Bypass HB1 First stage interpolation filter bypass. Rev Page HB1 . HB1 /2. Filter pass band is HB1 . HB1 /2. Filter pass band is HB1 . HB1 AD9148 Default Read- only Read- only Read- only Read- only Read- only 0 000 Read- only 0 ...
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... AD9148 Addr Register Name (Hex) Bit HB2 Control 1D 0 HB3 Control 1E 7 3:1 0 Chip ID 1F 7:0 Name Function HB2[2:0] Modulation mode for second stage interpolation filter ( × HB2 IN2 000 = input signal modulated by dc. Filter pass band is from −0 001 = input signal modulated by dc. Filter pass band is from 0 ...
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... Filter Coefficient 3 in twos complement Filter Coefficient 5 (LSB) in twos -1 Filter Coefficient 4 (MSB) in twos Filter Coefficient 5 (MSB) in twos Filter Coefficient 2 in twos complement Filter Coefficient 1 in twos complement Filter Coefficient 4 (LSB) in twos Filter Coefficient 3 in twos complement AD9148 Default ...
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... AD9148 Addr Register Name (Hex) Bit Coeff Q Byte 2 26 7:5 4 3:0 Coeff Q Byte 6:0 I Phase Adj LSB 28 7:0 I Phase Adj MSB 29 1:0 Q Phase Adj LSB 2A 7:0 Q Phase Adj MSB 2B 1 Offset LSB 2C 7 Offset MSB 2D 7 Offset LSB 2E 7 Offset MSB 2F 7:0 Name ...
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... AUX IDAC Auxiliary IDAC power-down. power-down AUX IDAC Data[9:8] Auxiliary IDAC data (MSB part). Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select =1 to configure DAC 3 path. Rev Page AD9148 Default ...
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... AD9148 Addr Register Name (Hex) Bit QDAC FSC Adj 34 7:0 QDAC Control 35 7 1:0 Aux QDAC Data 36 7:0 Aux QDAC Control 1:0 Name Function QDAC FSC Adj Q DAC full-scale current adjustment (LSB part). QDAC FS Adj[9:0] sets the full-scale current of the QDAC. The full-scale current can be adjusted from 8. 31 step sizes of approximately 22.5 µ ...
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... SED Compare Compare Pattern Sample3[15:0] is the word that is compared Pattern with Data Sample 3 captured at the input interface by the Sample3[15:8] falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. Rev Page AD9148 Default ...
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... AD9148 Addr Register Name (Hex) Bit SED Control/Status SED_R_L 41 7:0 SED_R_H 42 7:0 SED_F_L 43 7:0 SED_F_H 44 7:0 I Gain Control 50 7:0 Q Gain Control 51 7:0 Name Function SED compare enable Enables the SED circuitry. Port B error Status of last compare on Port B. detected Port A error Status of last compare on Port A. ...
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... Die Temp[7:0] Die Temp[15:0] indicates the approximate die temperature. Die Temp[15:8] Die Temp[15:0] indicates the approximate die temperature. DCI delay Programmable delay added DCI added delay 200 ps delay 400 ps delay 600 ps delay. Rev Page AD9148 Default ...
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... Figure 46. Timing Diagram for Dual-Port Mode, Two DCI Each data sample, by default, is expected to be formatted as an MSB sent to Bit 15 and an LSB sent to Bit 0 for each port. The AD9148 When this bus swap bit is set, the MSB should be sent to Bit 0, and the LSB should be sent to Bit 15 for each port. ...
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... By default, the Byte A[15:8] A[7:0] MSB Data Set 1[15:8] Data Set 2[15:8] LSB Data Set 1[7:0] Data Set 2[7:0] MSB Data Set 1[8:15] Data Set 2[8:15] LSB Data Set 1[0:7] Data Set 2[0:7] AD9148 150Ω FRAMEP 100Ω FRAMEN 51Ω DVDD18 (1.8V) Figure 49. External Bias Circuit ...
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... REG 7 Figure 50. Block Diagram of FIFO important to take into account when understanding the overall pipeline delay of the AD9148. In single-port and byte interface modes, the incoming digital data is sampled at twice the data rate (DCIA). The data is then assembled based on the interface mode. At the output of the data assembler ...
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... REGISTER 0x17[2:0] = 0b100 FRAMEA WRPTRA FIFO_B WRITE RESET FRAMEB WRPTRB Figure 52. Timing of the FRAME Input vs. Write Pointer Value in FIFO Rate Synchronization Rev Page AD9148 RESET VALUE FOR REGISTER 0x17[2:0] = 0b100 ...
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... Depending on the configuration of the system, the FIFO reset can be done manually or periodically for a multichip system. The AD9148 provides two ways to resetting the FIFO pointers: SPI interface or periodic reset using the FRAME signal. The SPI also gives access to each FIFO phase offset in Bits [2:0] of the corresponding FIFO status/control registers, Register 0x17 and Register 0x19 ...
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... The FRAME signal and DCI signals can be created in the FPGA along with the data. A circuit diagram of a typical configuration is shown in Figure 53. MATCHED LENGTH TRACES REFCLK/SYNC FRAME DCI LOW SKEW CLOCK DRIVER REFCLK/SYNC FRAME DCI MATCHED LENGTH TRACES Rev Page AD9148 OUT1 OUT2 ...
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... AD9148 The following procedure outlines the steps required to synchronize multiple devices. The procedure assumes that the REFCLK/SYNC signal is applied to all of the devices and the PLL of each device is phase locked to it. Each individual device must follow this procedure. The procedure for synchronization when using the PLL follows: 1 ...
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... N. Rev Page CLK REFCLK/SYNC OUT1 FRAME DCI CLK REFCLK/SYNC OUT2 FRAME DCI + t nanoseconds of each other. A timing SKEW OUTDLY t SKEW SU_DCI H_DCI SU_SYNC H_SYNC 2× Interpolation = ½ × The REFCLK/SYNC input DCI CLK f = DATA f SYNC N 2 AD9148 ...
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... AD9148 Generally, for values of N equal to or greater than 3, the FIFO rate synchronization mode is chosen. FIFO Rate Mode Synchronization The following procedure outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the CLK and REFCLK/SYNC signals are applied to all of the devices ...
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... DCI Delay 0.78 (Register 0x72,Bits[1:0]) 1. DATA SAMPLING INTERVAL SAMPLING INTERVAL Figure 59. Timing Diagram for Input Data Ports Rev Page AD9148 t DATA SAMPLING INTERVAL t SDCI t HDCI Minimum Setup Minimum Hold Time, t (ns) Time, t SDCI HDCI −0.06 0.85 −0.22 1.14 −0.36 1.43 − ...
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... The filter coefficients must be calculated and programmed into the AD9148 registers to perform the operation desired. Filter Implementation To perform the complex filtering of the complex input, the filter is divided in four filters working in parallel, two sets of H two sets of H (see Figure 61). ...
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... HB2 and HB3 filters each have eight modes of operation. Rev Page Maximum 011b 3 011b 3 0111b 7 0111b 7 01111b 15 01111b 15 0111111b 63 0111111b 63 0111111111b 1023 0111111111b 1023 ; − −35 5 Bandwidth of HB1 = 0.8 × f IN1 Bandwidth of HB2 = 0.5 × f IN2 Bandwidth of HB3 = 0.4 × f IN3 AD9148 ...
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... AD9148 Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 64. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center frequency and whether the filter modulates the input signal. MODE 0 ...
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... Filter Modes Pre-Mod HB1 HB2 AD9148 0.28 0.32 Stop-Band Rejection (dB CENTER HB3 (f ) DAC DAC DAC DAC ...
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... AD9148 Figure 69 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 24 shows the pass-band flatness and stop-band rejection the HB3 filter supports at different bandwidths ...
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... This allows the user to phase align the NCO output with some external signal, if necessary. This can be especially useful when NCOs of multiple AD9148s are programmed for synchronization. The phase offset allows for the adjustment of the output timing between the devices. ...
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... DAC noise performance. DIRECT CLOCKING When a high quality, sample rate clock is connected to the AD9148, it provides the lowest noise spectral density at the DAC outputs. To select the differential CLK inputs as the source for the DAC sampling clock, set the PLL enable bit to 0 (Register 0x0A, Bit 7) ...
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... Rev Page 0x0E[3:0] ADC PLL CONTROL VOLTAGE VCO DACCLK Bit Optimal Setting [7:5] 110 [4:0] 01001 [ 1000 1200 1400 1600 1800 VCO FREQUENCY (MHz) AD9148 2000 2200 ...
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... AD9148 Manual VCO Band Select The device also has a manual band select mode that allows the user to select the VCO tuning band. When in manual mode (enabled by setting Bit 6, Register 0x0A to 1), the VCO band is set directly with the value written to the manual VCO band bit enabled (Bits[5:0], Register 0x0A) ...
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... DAC SET 200 400 600 800 DAC GAIN CODE Figure 76. DAC Full-Scale Current vs. DAC Gain Code DACCODE = × I OUTFS – I OUTFS OUT_P N − 1. IOUT1_P/IOUT3_P IOUT1_N/IOUT3_N IOUT2_N/IOUT4_N IOUT2_P/IOUT4_P AD9148 1000 (1) (2) ...
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... The linear output signal swing is dependent on the full-scale output current, I AUXILIARY DAC OPERATION The AD9148 and AUX4). The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor. The gain scale from the reference amplifier current, I DAC reference current is 16.67 with the auxiliary DAC gain set to full-scale ...
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... IOUT1_N RSQN 1kΩ IOUT2_N RBQN RLQN 45.3Ω 3480Ω 5V RBQP RLQP RSQP 45.3Ω 3480Ω 1kΩ IOUT2_P Figure 82. Passive Level Shifting Network for Biasing the ADL5375-15 from the AD9148 3pF 100Ω ADL537x 6pF 3pF AD9148 ADL5375-15 IBBP IBBN QBBN QBBP ...
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... AD9148 Reducing LO Leakage and Unwanted Sidebands Analog Devices modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. This can be done either ...
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... Figure 87. DVDD18 Power Dissipation vs. f and Inverse Sinc Filter Disabled Rev Page AD9148 f (MSPS) DATA with Fine Modulation, PLL, and DATA Inverse Sinc Filter Disabled f (MSPS) DATA with Coarse Modulation, PLL, DATA f (MSPS) DATA with Fine Modulation, PLL, ...
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... AD9148 0.35 0.30 0.25 0.20 0.15 0.10 0. 100 200 300 400 500 600 f (MSPS) DAC Figure 88. CVDD18 Power Dissipation vs. f 700 800 900 1000 , PLL Disabled Figure 89. DVDD18 Power Dissipation vs. f DAC Rev Page 0.25 0.23 0.20 0.18 0.15 0.13 0.10 0.08 0.05 0. (MSPS) DATA Due to Inverse Sinc Filter DATA Data Sheet ...
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... Bit 0, Register 0x5C to 0. Before the temperature sensor data can be read back, it must be latched by toggling Bit 1, Register 0x5C from addition, to get accurate readings, the die temperature control register (Register 0x5D) should be set to 0x0A. Rev Page – P × – 0.8 × 35.6°C DIE shown in Table 7. AD9148 ...
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... AD9148 INTERRUPT REQUEST OPERATION The AD9148 provides an interrupt request output signal (Pin H4, IRQ ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output ...
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... Register 0x3D → S2[15:8] Register 0x3E → S3[7:0] Register 0x3F → S3[15:8] Register 0x00[4] → 1 (to configure Port B SED) Register 0x38 → S0[7:0] Register 0x39 → S0[15:8] Register 0x3A → S1[7:0] Register 0x3B → S1[15:8] Register 0x3C → S2[7:0] Register 0x3D → S2[15:8] Register 0x3E → S3[7:0] Register 0x3F → S3[15:8] AD9148 ...
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... AD9148 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9148, certain sequences should be followed. An example start-up routine using the following device configuration is used for this example. • 122.88 MSPS DATA • Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’ • ...
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... WITH EXCEPTION TO PACKAGE HEIGHT. Figure 93. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-196-7 Dimensions shown in millimeters Rev Page BALL CORNER BOTTOM VIEW 0.96 0.70 0.35 NOM 0.30 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER AD9148 ...
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... Chip Scale Package Ball Grid Array [CSP_BGA] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] DAC Only Evaluation Board [BGA_ED] AD9148 + ADL5372 Evaluation Board [BGA_ED] AD9148 + ADL5375-0.5 Evaluation Board [BGA_ED] Rev Page BALL PAD CORNER 14 ...
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... Data Sheet NOTES Rev Page AD9148 ...
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... AD9148 NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08910-0-1/12(B) Rev Page Data Sheet ...