AD5541A Analog Devices, AD5541A Datasheet - Page 15
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AD5541A
Manufacturer Part Number
AD5541A
Description
Manufacturer
Analog Devices
Datasheet
1.AD5541A.pdf
(20 pages)
Specifications of AD5541A
Resolution (bits)
16bit
Dac Update Rate
1MSPS
Dac Settling Time
1µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Unbuffered Vout
Dac Input Format
Ser,SPI
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UNIPOLAR OUTPUT OPERATION
This DAC is capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5541A provides a
unipolar output swing ranging from 0 V to V
Figure 31 shows a typical unipolar output voltage circuit. The
code table for this mode of operation is shown in Table 8. The
example includes the
low offset and zero-drift reference buffer.
Table 8. Unipolar Code Table
DAC Latch Contents
MSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
where:
V
D is the code loaded to DAC.
V
V
V
INL is the integral nonlinearity in volts.
OUT−UNI
REF
GE
ZSE
is the gain error in volts.
is the zero-scale error in volts.
is the reference voltage applied to the part.
V
OUT
is the unipolar mode worst-case output.
−
UNI
=
LSB
2
D
16
×
ADR421
(
V
5V
REF
Analog Output
V
V
V
0 V
REF
REF
REF
+
V
1µF
2.5 V reference and the
× (65,535/65,536)
× (32,768/65,536) = ½ V
× (1/65,536)
GE
)
+
0.1µF
V
ZSE
+
V
ADR421
REF
INL
2
IN
4
− 1 LSB.
V
OUT
INTERFACE
AD8628
REF
SERIAL
6
Figure 31. Unipolar Output
Rev. A | Page 15 of 20
AD8628
0.1µF
CS
DIN
SCLK
V
5V
DD
DGND
AD5541A
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±V
output. In a single-supply application, selection of a suitable
op amp may be more difficult because the output swing of the
amplifier does not usually include the negative rail, in this case,
AGND. This can result in some degradation of the specified
performance unless the application does not use codes near zero.
The selected op amp must have a very low offset voltage (the
DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 kΩ), adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, thus increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
REF
0.1µF
AGND
10µF
V
OUT
EXTERNAL
AD820/
OP196
OP AMP
UNIPOLAR
OUTPUT
AD5541A
REF