AD9739 Analog Devices, AD9739 Datasheet - Page 35

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
MULTIPLE DEVICE SYNCHRONIZATION
Synchronization of multiple AD9739s requires all of the devices
to have matching pipeline delays. This implies the DAC outputs
are time aligned to the same phase when all devices are fed with
the same data pattern at the same instance of time. The main
contributor to phase ambiguity between devices is from the
div-by-4 circuitry that drives the Rx data path and data controller
(see Figure 53). This phase ambiguity can result in a ±2 sample
offset between any two devices. Because the state of this internal
divider is unknown at power-up, a synchronization method that
phase aligns the digital paths of multiple AD9739s is required to
ensure matching pipeline delays.
Figure 52 shows a top-level diagram of multiple AD9739s
synchronized to each other with sample alignment of the
different data streams within the FPGA (or among multiple
FPGAs) being assumed. A common RF clock source is
distributed to each of the
buffer (such as the ADCLK946) with matched PCB trace
lengths to each device to ensure matched propagation delays.
FPGA_2
FPGA_1
MASTER
DCO
AD9739
REPEATER
SYNC_IN
SYNC_OUT
SYNC_OUT
DCI
DCI
DCI
devices via a dual clock
LVDS
DCO
DCO
DCO
1:N
AD9739
AD9739
AD9739
SLAVE_N
SLAVE_1
MASTER
Figure 52. Functional Block Diagram of Two AD9739s Synchronized
DACCLK
SYNC_OUT
DACCLK
DACCLK
SYNC_IN
SYNC_IN
MATCHED DELAYS
DCO
TO SLAVE_N
TO SLAVE_1
Rev. B | Page 35 of 48
TO FPGA_2
TO OTHER FPGAs
MATCHED DELAYS
MATCHED DELAYS
One
reference clock (equal to f
AD9739
matched output delays are again used to distribute the SYNC_OUT
and DCO signals of the master to the slave devices and FPGAs,
respectively, thus ensuring tight time alignment. Note, in the
case of a single FPGA implementation (that is, I/Q application),
the DCO of the master can drive the FPGA directly.
After synchronization, the internal div-by-4 circuitry will have
equal phases that drive their respective LVDS controllers. Note,
the mu and data receiver controller of both devices must be
configured for the same SPI register settings (that is, SET_PHS
and DCI_DEL) upon SPI initialization such that controllers
converge to similar delays. To validate that delays are roughly
matched, the user can read back the delays of both devices (that is,
MUDEL and DCI_DEL) to determine if they are in an acceptable
window that accounts for slight mismatches between different
devices’ delay lines.
AD9739
slave device’s SYNC_IN input. LVDS fanout buffers with
is designated as the master providing a SYNC_OUT
REPEATER
ADCLK346
LVDS
1:N
CLOCK SOURCE
DAC
COMMON
/4) to itself as well as the other
0.8GHz TO 2.0GHz
AD9739