AD5732 Analog Devices, AD5732 Datasheet
AD5732
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AD5732 Summary of contents
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... The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range. The AD5722/AD5732/AD5752 are pin compatible with the AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/ 16-bit, serial input, unipolar/bipolar voltage output DACs. ...
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... Load DAC ( LDAC )..................................................................... 20 Asynchronous Clear ( CLR )....................................................... 20 Configuring the AD5722/AD5732/AD5752 .......................... 20 REVISION HISTORY 7/11—Rev Rev. D Changes to Table 3: t7, t8, t10 Limits......................................................5 3/11—Rev Rev. C Changes to Configuring the AD5722/AD5732/AD5752 Section..20 8/10—Rev Rev. B Changes to Table 27........................................................................ 26 5/10—Rev Rev. A Changes to Junction Temperature, T max Parameter, Table Changes to Exposed Paddle Description, Table 5 ...
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... AD5752 16 AD5732 14 AD5722 12 Total Unadjusted Error (TUE) B Version −0.1 A Version −0.3 2 Integral Nonlinearity (INL) AD5752 A, B Versions −16 AD5732 A Version −4 AD5722 A Version −1 Differential Nonlinearity (DNL) −1 Bipolar Zero Error −6 3 Bipolar Zero TC Zero-Scale Error −6 Zero-Scale TC 3 Offset Error − ...
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... ICC 1 For specified performance, the maximum headroom requirement is 0 INL is the relative accuracy measured from Code 512, Code 128, and Code 32 for the AD5752, the AD5732, and the AD5722, respectively. 3 Guaranteed by characterization; not production tested. Typ Max Unit V 0.8 V ± ...
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... SYNC rising edge to SCLK falling edge ns max SCLK rising edge to SDO valid (C ns min Minimum SYNC high time (readback/daisy-chain mode) ) and timed from a voltage level of 1 Rev Page AD5722/AD5732/AD5752 = 2 5 kΩ; CC LOAD Test Conditions/Comments 20 V step to ±0.03% FSR 10 V step to ±0.03% FSR ...
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... AD5722/AD5732/AD5752 TIMING DIAGRAMS SCLK SYNC t 7 SDIN DB23 t 9 LDAC V x OUT V x OUT CLR V x OUT SCLK SYNC t 7 D32B SDIN SDO LDAC DB0 Figure 2. Serial Interface Timing Diagram ...
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... SCLK 1 SYNC DB23 SDIN INPUT WORD SPECIFIES REGISTER TO BE READ DB23 SDO UNDEFINED DB0 DB23 NOP CONDITION DB0 DB23 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram Rev Page AD5722/AD5732/AD5752 24 DB0 DB0 ...
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... AD5722/AD5732/AD5752 ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. A Transient currents 100 mA do not cause SCR latch-up. Table 4. Parameter Rating AV to GND −0 + GND +0 − GND −0 Digital Inputs to GND −0 ...
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... NOTES CONNECT RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration , input coding is offset binary. When hardwired to GND, input coding is twos CC Rev Page AD5722/AD5732/AD5752 or GND. CC pin, or alternatively, it can be left electrically SS ...
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... Figure 8. AD5722 Integral Nonlinearity Error vs. Code 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 50,000 60,000 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 Figure 10. AD5732 Differential Nonlinearity Error vs. Code 0.04 0.03 0.02 0.01 –0.01 –0.02 –0.03 –0.04 –0.05 3000 3500 4000 Figure 11. AD5722 Differential Nonlinearity Error vs. Code Rev Page /AV = +12V/0V, RANGE = +10V DD ...
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... Figure 16. AD5752 Differential Nonlinearity Error vs. Supply Voltage 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 15.5 16.0 16.5 5.5 Figure 17. AD5752 Differential Nonlinearity Error vs. Supply Voltage Rev Page AD5722/AD5732/AD5752 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) BIPOLAR 10V MIN UNIPOLAR 10V MIN BIPOLAR 10V MAX UNIPOLAR 10V MAX 12.0 12.5 13 ...
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... AD5722/AD5732/AD5752 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 11.5 12.0 12.5 13.0 13.5 14.0 14.5 SUPPLY VOLTAGE (V) Figure 18. AD5752 Total Unadjusted Error vs. Supply Voltage 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) Figure 19. AD5752 Total Unadjusted Error vs. Supply Voltage (mA –1 AI (mA) –2 DD –3 –4 4.5 6.5 8.5 10.5 AV /AV ( Figure 20. Supply Current vs. Supply Voltage (Dual Supply) ...
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... Figure 28. Full-Scale Settling Time, ±5 V Range – Figure 29. Full-Scale Settling Time, +10 V Range Rev Page AD5722/AD5732/AD5752 – TIME (µs) – TIME (µs) – ...
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... AD5722/AD5732/AD5752 –3 – TIME (µs) Figure 30. Full-Scale Settling Time Range 0.020 ±10V RANGE, 0x7FFF TO 0x8000 ±10V RANGE, 0x8000 TO 0x7FFF ±5V RANGE, 0x7FFF TO 0x8000 0.015 ±5V RANGE, 0x8000 TO 0x7FFF +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF ...
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... /AV = +6.5V/0V, RANGE = + –2 –4 –6 –8 –10 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 36. AD5732 Total Unadjusted Error vs. Code AD5722/AD5732/AD5752 1.0 AV /AV = +12V/0V, RANGE = +10V /AV = ±12V, RANGE = ±10V /AV = ±6.5V, RANGE = ± 0 ...
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... A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5722/ AD5732/AD5752 are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ...
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... DAC but is measured when the DAC output is not updated specified in nV-sec and measured with a full-scale code change on the data bus. AD5722/AD5732/AD5752 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC ...
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... V to ±16 addition, the parts have software-selectable output ranges +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the AD5722/AD5732/ AD5752 in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy-chaining or readback ...
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... Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5722/AD5732/AD5752 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register ...
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... SDO TRANSFER FUNCTION Table 7 to Table 15 show the relationships of the ideal input code to output voltage for the AD5752, AD5732, and AD5722, respectively, for all output voltage ranges. For unipolar output ranges, the data coding is straight binary. For bipolar output ranges, the data coding is user selectable via the BIN/ 2sCOMP pin and can be either offset binary or twos complement ...
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... REFIN × (1/65,536) 0000 0000 0000 0000 0 V AD5722/AD5732/AD5752 Analog Output ±10 V Output Range +4 × REFIN × (32,767/32,768) +4 × REFIN × (32,766/32,768) … +4 × REFIN × (1/32,768 −4 × REFIN × (1/32,768) … ...
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... AD5722/AD5732/AD5752 Ideal Output Voltage to Input Code Relationship—AD5732 Table 10. Bipolar Output, Offset Binary Coding Digital Input MSB LSB 11 1111 1111 1111 11 1111 1111 1110 … … … … 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 … … … … ...
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... REFIN × (1/4096) 0000 0000 0000 0 V AD5722/AD5732/AD5752 Analog Output ±10 V Output Range +4 × REFIN × (2047/2048) +4 × REFIN × (2046/2048) … +4 × REFIN × (1/2048 −4 × REFIN × (1/2048) … −4 × REFIN × (2046/2048) − ...
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... AD5722/AD5732/AD5752 INPUT SHIFT REGISTER The input shift register is 24 bits wide and consists of a read/write bit ( reserved bit (zero) that must always be set to 0, three register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin ...
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... The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel in which the data transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5752 (see Table 18), DB15 to DB2 for the AD5732 (see Table 19), and DB15 to DB4 for the AD5722 (see Table 20). Table 18. Programming the AD5752 DAC Register ...
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... The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5722/AD5732/AD5752. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register ...
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... G1 G2 Figure 42. Analog Output Control Circuitry POWER-DOWN MODE Each DAC channel of the AD5722/AD5732/AD5752 can be individually powered down. By default, all channels are in power-down mode. The power status is controlled by the power control register (see Table 26 and Table 27 for details). When a channel is in power-down mode, its output pin is clamped to ground through a resistance of approximately 4 kΩ ...
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... The printed circuit board on which the AD5722/AD5732/AD5752 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5722/AD5732/AD5752 are in a system where multiple devices require an AGND-to- DGND connection, the connection should be made at one point only ...
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... The AD5722/ AD5732/AD5752 require a 24-bit data-word with data valid on the falling edge of SCLK. Table 28. Some Precision References Recommended for Use with the AD5722/AD5732/AD5752 Part No. Initial Accuracy (mV max) ADR431 ± ...
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... TOP VIEW 1.20 MAX 0.15 0.65 SEATING 0.05 BSC PLANE 0.10 COPLANARITY Figure 45. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] ORDERING GUIDE 1 Model Resolution (Bits) AD5722AREZ 12 AD5722AREZ-REEL7 12 AD5732AREZ 14 AD5732AREZ-REEL7 14 AD5752AREZ 16 AD5752AREZ-REEL7 RoHS Compliant Part. 5.02 5.00 4.95 13 4.50 EXPOSED 4.40 PAD (Pins Up) 4.30 6.40 BSC 12 BOTTOM VIEW 1.05 1.00 8° 0.80 0° ...
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... NOTES AD5722/AD5732/AD5752 Rev Page ...
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... AD5722/AD5732/AD5752 NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06467-0-7/11(D) Rev Page ...