AD5764R Analog Devices, AD5764R Datasheet - Page 23

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AD5764R

Manufacturer Part Number
AD5764R
Description
Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5764R

Resolution (bits)
16bit
Dac Update Rate
1MSPS
Dac Settling Time
8µs
Max Pos Supply (v)
+16.5V
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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Data Sheet
See Figure 41 for a simplified block diagram of the DAC load
circuitry.
TRANSFER FUNCTION
Table 7 and Table 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectively.
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
MSB
1111
1000
1000
0111
0000
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
MSB
0111
0000
0000
1111
1000
REFAB, REFCD
Figure 41. Simplified Serial Interface of Input Loading Circuitry
LDAC
SYNC
SCLK
SDIN
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
for One DAC Channel
INTERFACE
REGISTER
REGISTER
16-BIT
DAC
INPUT
DATA
LOGIC
Digital Input
Digital Input
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
I/V AMPLIFIER
OUTPUT
SDO
VOUTx
1111
0001
0000
1111
0000
1111
0001
0000
1111
0000
Rev. D | Page 23 of 32
LSB
LSB
The output voltage expression for the
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time for the operation to complete
(see Figure 2). When the CLR signal is returned high, the output
remains at the cleared value until a new value is programmed.
If CLR is at 0 V at power-on, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing the command of 0x04XXXX.
REFIN
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
OUT
OUT
V
is the reference voltage applied at the REFAB and
OUT
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
=
× (32,767/32,768)
× (1/32,768)
× (1/32,768)
× (32,767/32,768)
× (32,767/32,768)
× (1/32,768)
× (1/32,768)
× (32,767/32,768)
2
×
V
REFIN
+
4
×
V
REFIN
65
AD5764R
D
,
536
is given by
AD5764R

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