AD9785 Analog Devices, AD9785 Datasheet - Page 37

• Manufacturer Part Number: AD9785
• Description: Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO
• Manufacturer: Analog Devices

Specifications of AD9785

• Resolution (bits): 12bit
• Dac Update Rate: 800MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

Manual Timing Optimization Mode
When the device is operating in manual timing optimization
mode (Register 0x02, Bit 3 = 0), the device does not alter the
DATACLK Delay [4:0] value that is programmed by the user. By
default, the DATACLK delay enable is inactive. This bit must be
set high for the DATACLK Delay [4:0] value to be realized.
The delay (in absolute time) when programming the DATACLK
delay from 00000 to 11111 varies from about 700 ps to about
6.5 ns. Typical delays per increment over temperature are shown
in Table 27.
Table 27. Data Delay Line Typical Delays over Temperature
Delay
Zero code delay (delay upon
enabling delay line)
Average unit delay
In manual mode, the error checking logic is activated and
generates an interrupt if a setup/hold violation is detected. One
error check operation is performed per device configuration.
Any change to the Data Timing Margin [3:0] or DATACLK
Delay [4:0] values triggers a new error check operation.
INPUT DATA RAM
The AD9785/AD9787/AD9788 feature on-chip RAM that can
be used as an alternative input data source to the input data pins.
The input data RAM is loaded through the SPI port. After the
input data is stored in memory, the device can be configured to
transmit the stored data instead of receiving data through the
input data pins. This can be a useful test mode for factory or
in-system testing.
The RAM is 64 words long and 32 bits wide. The 16 MSBs drive
the I datapath, and the 16 LSBs drive the Q datapath. The RAM
configuration is shown in Figure 54.
64 WORDS
0x1D
Figure 54. Input Data RAM Configuration
16 BITS
I-SIDE
−40°C
630
175
32 BITS
+25°C
700
190
16 BITS
Q-SIDE
+85°C
740
210
Unit
ps
ps
Rev. A | Page 37 of 64
The data can be written to the RAM in either LSB first or MSB
first format.
To write to the RAM in MSB first format, complete the
following steps:
1.
2.
After the instruction byte (a write to Register 0x1D) is received,
the device automatically generates the addresses required to write
the RAM, starting at the most significant address. The 32 rising
SCLK edges following the instruction byte write the first RAM
word. At this time, the internal address generator decrements
and the next 32 rising edges of SCLK write the second RAM
word. This cycle of decrementing the RAM address and writing
32-bit words continues until the last word is written. After the
64th word is written, the communication cycle is complete.
To write to the RAM in LSB first format, complete the following
steps:
1.
2.
All memory elements must be accessed to complete a commu-
nication cycle. Note that the RAM is not a dual-port memory
element; therefore, if an I/O operation is begun while the RAM
is being used to drive data into the signal processing path, the
I/O operation has priority.
To begin using the RAM as an internal data generator, set
Register 0x1E (test register) to a value of 0x00C000. After these
24 bits are written, the DAC starts to output the waveform
stored in memory.
Set Bit 6 of Register 0x00 to 0.
Apply an instruction byte of 0xEE followed by the data to
be stored.
Set Bit 6 of Register 0x00 to 1.
Apply an instruction byte of 0xEE followed by the data to
be stored.
AD9785/AD9787/AD9788