AD9787 Analog Devices, AD9787 Datasheet - Page 41

• Manufacturer Part Number: AD9787
• Description: Dual 14-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO
• Manufacturer: Analog Devices

Specifications of AD9787

• Resolution (bits): 14bit
• Dac Update Rate: 800MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

Table 31. Inverse Sinc Filter
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
The inverse sinc filter is disabled by default. It can be enabled by
setting the inverse sinc enable bit (Bit 9) in Register 0x01.
DIGITAL AMPLITUDE AND OFFSET CONTROL
The gain of the I datapath and the Q datapath can be independ-
ently scaled by adjusting the I DAC Amplitude Scale Factor [8:0]
or Q DAC Amplitude Scale Factor [8:0] value in Register 0x0C.
These values control the input to a digital multiplier. The value
of the scale factor ranges from 0 to 3.9921875 and can be
calculated as follows:
The digital scale factor can be used to compensate for amplitude
imbalance between the I and Q channels or to provide equal
gain scaling to both channels for output level adjustment. Note
that when the gain is set to 1.0 (scale factor = 0x80), the gain
block is bypassed. When bypassed, the gain block has a different
delay from when it is used. Therefore, to maintain matched
latency in each path, both gain blocks should be set to exactly
1.0, or neither path should be set to exactly 1.0. Failing to
maintain matched latencies in the I and Q paths creates a phase
imbalance in quadrature signals, which results in poor sideband
suppression of upconverted signals.
The dc value of the I datapath and the Q datapath can also be
independently controlled. This is accomplished by adjusting
the I DAC Offset [15:0] and Q DAC Offset [15:0] values in
Register 0x0D. These values are added directly to the datapath
values. Care should be taken not to overrange the transmitted
values.
Figure 59 shows how the DAC offset current varies as a function
of the I DAC Offset [15:0] and Q DAC Offset [15:0] values. With
the digital inputs fixed at midscale (0x0000, twos complement
data format), the figure shows the nominal I
currents as the DAC offset value is swept from 0 to 65535.
Because I
the sum of I
Scale
OUTx_P
Factor
OUTx_P
and I
Value
and I
OUTx_N
OUTx_N
Upper Coefficient
H(9)
H(8)
H(7)
H(6)
–

Scale
are complementary current outputs,
is always 20 mA.
Factor
128
[
: 8
] 0
OUTx_P
Integer Value
+2
−4
+10
−35
+401
and I
OUTx_N
Rev. A | Page 41 of 64
The offset currents generated by the DAC offset parameter
increase from 0 mA to 10 mA as the offset is swept from 0 to
0x7FFF. The offset currents increase from −10 mA to 0 mA as
the offset is swept from 0x8000 to 0xFFFF.
DIGITAL PHASE CORRECTION
The purpose of the phase correction block is to enable compens-
ation of the phase imbalance of the analog quadrature modulator
following the DAC. If the quadrature modulator has a phase
imbalance, the unwanted sideband appears with significant
energy. Adjusting the phase correction word can optimize image
rejection in single sideband radios.
Ordinarily the I and Q channels have an angle of precisely 90°
between them. The Phase Correction Word [9:0] (Register 0x0B)
is used to change the angle between the I and Q channels. When
the Phase Correction Word [9:0] is set to 1000000000b, the
Q DAC output moves approximately 14° away from the I DAC
output, creating an angle of 104° between the channels. When
the Phase Correction Word [9:0] is set to 0111111111b, the
Q DAC output moves approximately 14° towards the I DAC
output, creating an angle of 76° between the channels. Based on
these two endpoints, the resolution of the phase compensation
register is approximately 28°/1024 or 0.027° per code.
0x0000
20
15
10
5
0
Figure 59. DAC Output Currents vs. DAC Offset Value
0x4000
DAC OFFSET VALUE
AD9785/AD9787/AD9788
0x8000
0xC000
0xFFFF
0
5
10
15
20