AD9780 Analog Devices, AD9780 Datasheet - Page 21

• Manufacturer Part Number: AD9780
• Description: Dual 12-Bit, LVDS Interface 500 MSPS DAC
• Manufacturer: Analog Devices

Specifications of AD9780

• Resolution (bits): 12bit
• Dac Update Rate: 500MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 12.
Register
SPI Control
Data Control
Power-Down
Setup and Hold
Timing Adjust
Seek
Mix Mode
DAC1 FSC
Address
0x00
0x02
0x03
0x04
0x05
0x06
0x0A
0x0B
0x0C
Bit
7
6
5
7
4
7
6
5
4
3
2
1
0
7:4
3:0
4:0
2
1
0
3:2
1:0
7:0
1:0
Name
SDIO_DIR
LSBFIRST
RESET
DATA
INVDCO
PD_DCO
PD_INPT
PD_AUX2
PD_AUX1
PD_BIAS
PD_CLK
PD_DAC2
PD_DAC1
HLD[3:0]
SAMP_DLY[4:0]
LVDS low
LVDS high
SEEK
DAC1MIX[1:0]
DAC2MIX[1:0]
DAC1FSC[9:0]
SET[3:0]
Function
0, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin.
1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line.
0, MSB first per SPI standard.
1, LSB first per SPI standard.
Only change LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
0, execute software reset of SPI and controllers, reload default register values
except Register 0x00.
1, set software reset, write 0 on the next (or any following) cycle to release the reset.
0, DAC input data is twos complement binary format.
1, DAC input data is unsigned binary format.
1, inverts the data clock output. Used for adjusting timing of input data.
1, power down data clock output driver circuit.
1, power down input.
1, power down AUX2 DAC
1, power down AUX1 DAC.
1, power down voltage reference bias circuit.
1, power down DAC clock input circuit.
1, power down DAC2.
1, power down DAC1.
4-bit value used to determine input data setup timing.
4-bit value used to determine input data hold timing.
5-bit value used to optimally position input data relative to internal sampling clock.
One of the LVDS inputs is above the input voltage limits of the IEEE reduced link
specification.
One of the LVDS inputs is below the input voltage limits of the IEEE reduced link
specification.
Indicator bit used with LVDS_SET and LVDS_HLD to determine input data timing
margin.
00, selects normal mode, DAC1.
01, selects return-to-zero mode, DAC1.
10, selects return-to-zero mode, DAC1.
11, selects mix mode, DAC1.
00, selects normal mode, DAC2.
01, selects return-to-zero mode, DAC2.
10, selects return-to-zero mode, DAC2.
11, selects mix mode, DAC2.
DAC1 full-scale 10-bit adjustment word.
0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.
0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.
Rev. A | Page 21 of 36
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