AD5666 Analog Devices, AD5666 Datasheet - Page 22

• Manufacturer Part Number: AD5666
• Manufacturer: Analog Devices

Specifications of AD5666

• Resolution (bits): 16bit
• Dac Update Rate: 95kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5666
INPUT SHIFT REGISTER
The input shift register is 32 bits wide (see Figure 42). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 9) and finally the 16-bit data-word.
The data-word comprises the 16-bit input code followed by four
don’t care bits for the AD5666 (see Figure 42). These data bits
are transferred to the DAC register on the 32
SCLK.
DB31 (MSB)
X
SYNC
SCLK
X
DIN
X
SYNC HIGH BEFORE 32ND FALLING EDGE
X
C3
DB31
INVALID WRITE SEQUENCE:
COMMAND BITS
C2
C1
C0
A3
ADDRESS BITS
A2
DB0
A1
nd
falling edge of
A0
Figure 42. AD5666 Input Register Content
D15 D14 D13 D12 D11 D10
Figure 43. SYNC Interrupt Facility
Rev. D | Page 22 of 28
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32
32
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
nd
nd
VALID WRITE SEQUENCE, OUTPUT UPDATES
D9
falling edge. However, if SYNC is brought high before the
falling edge, this acts as an interrupt to the write sequence.
D8
DATA BITS
DB31
ON THE 32ND FALLING EDGE
D7
D6
D5
D4
D3
DB0
D2
D1
Figure 43
D0
X
X
).
DB0 (LSB)
X
X