AD5641 Analog Devices, AD5641 Datasheet - Page 14

• Manufacturer Part Number: AD5641
• Description: 2.7 V to 5.5 V,
• Manufacturer: Analog Devices

Specifications of AD5641

• Resolution (bits): 14bit
• Dac Update Rate: 1.7MSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5641
POWER-ON RESET
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
0s and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions in which it is important to know the state of the DAC
output while it is in the process of powering up.
POWER-DOWN MODES
The AD5641 has four separate modes of operation. These
modes are software programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
Table 6. Operating Modes for the AD5641
DB15
0
0
1
1
When both bits are set to 0, the part has normal power
consumption of 100 µA maximum at 5 V. However, for the
three power-down modes, the supply current falls to typically
0.2 µA at 3 V.
SCLK
SYNC
SDIN
DB14
0
1
0
1
SYNC HIGH BEFORE 16
DB15
INVALID WRITE SEQUENCE:
DB15 (MSB)
PD1
PD0
Operating Mode
Normal operation
Power-down mode:
1 kΩ to GND
100 kΩ to GND
Three-state
TH
D13
0
0
1
1
FALLING EDGE
DB0
0
1
0
1
D12
NORMAL OPERATION
1 kΩ TO GND
100 kΩ TO GND
THREE-STATE
D11
D10
Figure 35. Input Register Contents
Figure 36. SYNC Interrupt Facility
D9
POWER-DOWN MODES
Rev. D | Page 14 of 20
D8
DATA BITS
D7
Not only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or the output is left open-circuited
(three-stated). Figure 37 shows the output stage.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 13 µs for V
See Figure 29 for a plot.
D6
VALID WRITE SEQUENCE, OUTPUT UPDATES
D5
STRING DAC
DB16
RESISTOR
ON THE 16
D4
Figure 37. Output Stage During Power-Down
D3
TH
FALLING EDGE
D2
POWER-DOWN
AMPLIFIER
CIRCUITRY
DD
DB0
D1
DB0 (LSB)
= 5 V and 16 µs for V
D0
RESISTOR
NETWORK
Data Sheet
V
DD
OUT
= 3 V.