AD5339 Analog Devices, AD5339 Datasheet
AD5339
Specifications of AD5339
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AD5339 Summary of contents
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... V to 5.5 V, 250 μA, 2-Wire Interface, Dual Voltage Output, 8-/10-/12-Bit DACs GENERAL DESCRIPTION The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit buffered voltage output DACs, respectively. Each part is housed in an 8-lead MSOP package and operates from a single 2 5.5 V supply, consuming 250 μ On-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/μ ...
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... AD5337/AD5338/AD5339 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Characteristics........................................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 15 Digital-to-Analog Converter Section ...................................... 15 Resistor String ............................................................................. 15 DAC Reference Inputs ............................................................... 15 REVISION HISTORY 9/07— ...
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... V − V − 0.001 0.001 0.5 0 2.5 2 Rev Page AD5337/AD5338/AD5339 unless otherwise noted. MIN MAX 1 Max Unit Conditions/Comments Bits ±0.5 LSB ±0.25 LSB Guaranteed monotonic by design over all codes Bits ±2 LSB ±0.50 LSB Guaranteed monotonic by ...
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... See the Terminology section for explanations of the specific parameters specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981). 5 Guaranteed by design and characterization; not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative ...
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... V/μs 12 nV-s 1 nV-s 1 nV-s 3 nV-s 200 kHz −70 dB Rev Page AD5337/AD5338/AD5339 unless otherwise noted. MAX Conditions/Comments REF DD 1/4 scale to 3/4 scale change (0x40 to 0xC0) 1/4 scale to 3/4 scale change (0x100 to 0x300) 1/4 scale to 3/4 scale change (0x400 to 0xC00) 1 LSB change around major carry ± 0.1 V p-p ...
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... AD5337/AD5338/AD5339 TIMING CHARACTERISTICS 5.5 V. All specifications T DD Table 3. Limit MIN MAX Parameter A Version and B Version f 400 SCL 100 300 250 11 0 300 0 400 master device must provide a hold time of at least 300 ns for the SDA signal (referred to V ...
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... Exposure to absolute + 0 maximum rating conditions for extended periods may affect + 0 device reliability Transient currents 100 mA do not cause SCR latch-up ESD CAUTION ) θ Rev Page AD5337/AD5338/AD5339 ...
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... Clock rates 400 kbps can be accommodated in the 2-wire interface Address Input. Sets the least significant bit of the 7-bit slave address AD5337/ DD AD5338 SCL 2 7 OUT AD5339 V B SDA 3 6 OUT TOP VIEW REFIN GND 4 5 (Not to Scale) Figure 3. Pin Configuration Rev Page ...
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... CODE Figure 5. AD5338 Typical INL Plot 25° –4 –8 –12 0 500 1000 1500 2000 2500 CODE Figure 6. AD5339 Typical INL Plot 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 200 250 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 800 1000 1.0 0.5 0 –0.5 –1.0 3000 ...
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... AD5337/AD5338/AD5339 0. 25° 0.25 MAX DNL MAX INL 0 MIN DNL –0.25 MIN INL –0.50 0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF Figure 10. AD5337 INL and DNL Error vs REF 0.3 0.2 0.1 MAX DNL 0 –0.1 –0.2 MIN INL –0.3 –0.4 –0.5 – TEMPERATURE (°C) Figure 11. AD5337 INL and DNL Error vs. Temperature 1 ...
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... CH1 CH2 4.5 5.0 5.5 CH1 –40°C CH2 +105°C 4.5 5.0 5.5 CH1 CH2 3.5 4.0 4.5 5.0 Rev Page AD5337/AD5338/AD5339 T = 25° REF V A OUT SCL CH1 1V, CH2 5V, TIME BASE = 1µs/DIV Figure 19. Midscale Settling (¼ to ¾ Scale Code Change 25° ...
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... 150 200 250 I (µA) DD Figure 22. I Histogram with and 2.50 2.49 2.48 2.47 1µs/DIV Figure 23. AD5339 Major Code Transition Glitch Energy 10 0 –10 –20 –30 –40 –50 –60 10 100 1k 10k FREQUENCY (Hz) Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response –0.01 –0.02 ...
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... The difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonic distortion present in the DAC output measured in dB. Rev Page AD5337/AD5338/AD5339 ...
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... AD5337/AD5338/AD5339 OUTPUT IDEAL VOLTAGE ACTUAL NEGATIVE OFFSET DAC CODE ERROR DEADBAND CODES AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 27. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE POSITIVE OFFSET Rev Page GAIN ERROR PLUS OFFSET ERROR ...
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... OUT POWER-ON RESET OUTPUT BUFFER AMPLIFIER The AD5337/AD5338/AD5339 power defined state via a power-on reset function. The power-on state is normal operation, with output voltage set Both input and DAC registers are filled with zeros until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering on ...
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... AD5338/AD5339 DACs. This interface is SMBus compatible at V < 3 The AD5337/AD5338/AD5339 have a 7-bit slave address. The six MSBs are 000110, and the LSB is determined by the state of the A0 pin. The facility of making hardwired changes to A0 allows the use of one or two of these devices on one bus. The AD5338-1 has a unique 7-bit slave address ...
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... CLR , which is 1. WRITE OPERATION When writing to the AD5337/AD5338/AD5339 DACs, the user must begin with an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low ...
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... AD5337/AD5338/AD5339 READ OPERATION When reading data back from the AD5337/AD5338/AD5339 DACs, the user begins with an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte is usually followed by the pointer byte, which is also acknowledged by the DAC. Then, the master initiates another start condition (repeated start) and the address is resent with ...
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... LDAC was brought low, thereby removing unnecessary digital crosstalk. POWER-DOWN MODES The AD5337/AD5338/AD5339 have very low power consumption, typically dissipating 0.75 mW with supply and 1.5 mW with supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bit 15 and Bit 14 (PD1 and PD0) of the data byte ...
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... REFIN is the reference voltage input. With REFIN = kΩ: MULTIPLE DEVICES ON ONE BUS Figure 38 shows two AD5339 devices on the same serial bus. Each has a different slave address because the state of the A0 pin is different. This allows each of four DACs to be written to or read from independently ...
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... The printed circuit board on which the AD5337/AD5338/AD5339 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5337/AD5338/AD5339 are in a system where multiple devices require an AGND-to- DGND connection, the connection should be made at one 1kΩ ...
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... AD5321 12 1 Dual AD5302 8 2 AD5312 10 2 AD5322 12 2 AD5303 8 2 AD5313 10 2 AD5323 12 2 AD5337 8 2 AD5338 10 2 AD5338 AD5339 12 2 Quad AD5304 8 4 AD5314 10 4 AD5324 12 4 AD5305 8 4 AD5315 10 4 AD5325 12 4 AD5306 8 4 AD5316 10 4 AD5326 12 4 ...
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... Rev Page AD5337/AD5338/AD5339 HBEN CLR Package No. of Pins * TSSOP 20 * TSSOP 20 * TSSOP TSSOP 20 * TSSOP 20 * TSSOP 24 * TSSOP TSSOP 20 * TSSOP TSSOP 24 * TSSOP 28 TSSOP 28 * TSSOP, LFCSP 38 TSSOP, LFCSP ...
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... AD5339ARMZ −40°C to +105°C 1 AD5339ARMZ-REEL7 −40°C to +105°C AD5339BRM −40°C to +105°C AD5339BRM-REEL −40°C to +105°C AD5339BRM-REEL7 −40°C to +105°C 1 AD5339BRMZ −40°C to +105°C 1 AD5339BRMZ-REEL −40°C to +105°C 1 AD5339BRMZ-REEL7 −40°C to +105° RoHS Compliant Part ...
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... NOTES AD5337/AD5338/AD5339 Rev Page ...
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... AD5337/AD5338/AD5339 NOTES Rev Page ...
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... NOTES AD5337/AD5338/AD5339 Rev Page ...
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... AD5337/AD5338/AD5339 NOTES Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips © ...