AD5321 Analog Devices, AD5321 Datasheet - Page 14

• Manufacturer Part Number: AD5321
• Description: 2.5 V to 5.5 V, 120 µA, 2-Wire Interface, Voltage-Output 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5321

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5301/AD5311/AD5321
SERIAL INTERFACE
2-WIRE SERIAL BUS
The AD5301/AD5311/AD5321 are controlled via an I
compatible serial bus. The DACs are connected to this bus
as slave devices (no clock is generated by the AD5301/AD5311/
AD5321 DACs).
The AD5301/AD5311/AD5321 has a 7-bit slave address. In
the case of the 6-lead device, the six MSBs are 000110 and the
LSB is determined by the state of the A0 pin. In the case of the
8-lead device, the five MSBs are 00011 and the two LSBs are
determined by the state of the A0 and A1 pins. A1 and A0
allow the user to use up to four of these DACs on one bus.
The 2-wire serial bus protocol operates as follows:
1.
2.
3.
The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte that consists of the 7-bit slave address
followed by an R/ W bit (this bit determines whether data
is read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/ W bit is high, the master reads
from the slave device. However, if the R/ W bit is low, the
master writes to the slave device.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
When all data bits have been read or written, a stop con-
dition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
DB15 (MSB)
DB15 (MSB)
DB15 (MSB)
X
X
X
X
X
X
PD1 PD0
PD1 PD0
PD1 PD0 D11
Figure 26. AD5301 Input Shift Register Contents
Figure 27. AD5311 Input Shift Register Contents
Figure 28. AD5321 Input Shift Register Contents
D7
D9
2
C-
D10
D6
D8
D5
D7
D9
Rev. B | Page 14 of 24
DATA BITS
D4
D6
D8
DATA BITS
D3
D7
D5
DATA BITS
D2
D4
D6
In the case of the AD5301/AD5311/AD5321, a write operation
contains two bytes whereas a read operation may contain one or
two bytes. See Figure 29 to Figure 34 for a graphical explanation
of the serial interface.
A repeated write function gives the user flexibility to update the
DAC output a number of times after addressing the part only
once. During the write cycle, each multiple of two data bytes
updates the DAC output. For example, after the DAC acknowl-
edges its address byte, and receives two data bytes; the DAC
output updates after the two data bytes, if another two data
bytes are written to the DAC while it is still the addressed slave
device. These data bytes also cause an output update. A repeat
read of the DAC is also allowed.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Figure 26, Figure 27,
and Figure 28 illustrate the contents of the input shift register
for each part. Data is loaded into the device as a 16-bit word
under the control of a serial clock input, SCL. The timing
diagram for this operation is shown in Figure 2. The 16-bit
word consists of four control bits followed by 8/10/12 bits of
data, depending on the device type. MSB (Bit 15) is loaded first.
The first two bits are don’t cares. The next two are control bits
that control the mode of operation of the device (normal mode
or any one of three power-down modes). See the Power-Down
Modes section for a complete description. The remaining bits
are left justified DAC data bits, starting with the MSB and
ending with the LSB.
D1
D3
D5
SCL is high. In write mode, the master pulls the SDA line
high during the 10
tion. In read mode, the master issues a no acknowledge for
the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the 10
clock pulse and then high during the 10
establish a stop condition.
D0
D2
D4
D1
D3
X
D0
D2
X
DB0 (LSB)
DB0 (LSB)
DB0 (LSB)
D1
X
X
th
clock pulse to establish a stop condi-
D0
X
X
th
clock pulse to
th