AD5321 Analog Devices, AD5321 Datasheet - Page 5

• Manufacturer Part Number: AD5321
• Description: 2.5 V to 5.5 V, 120 µA, 2-Wire Interface, Voltage-Output 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5321

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AC CHARACTERISTICS
V
Table 2.
Parameter
Output Voltage Settling Time
Slew Rate
Major-Code Change Glitch Impulse
Digital Feedthrough
1
2
3
TIMING CHARACTERISTICS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
5
SCL
1
2
3
4
5
6
7
8
9
10
11
See the Terminology section.
Temperature range for the B Version is as follows: –40°C to +105°C.
Guaranteed by design and characterization, not production tested.
See Figure 2.
Guaranteed by design and characterization, not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the V
falling edge.
t
C
b
3
R
DD
DD
b
AD5301
AD5311
AD5321
and t
is the total capacitance of one bus line in picofarads.
= 2.5 V to 5.5 V; R
= 2.5 V to 5.5 V; all specifications T
F
SDA
SCL
measured between 0.3 V
3
2
(B Version)
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1C
400
Limit at T
t
9
L
= 2 kΩ to GND; C
CONDITION
b
5
START
1
DD
MIN
t
4
and 0.7 V
, T
MAX
1
t
3
DD
.
MIN
L
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
to T
= 200 pF to GND; all specifications T
Min
t
10
MAX
Figure 2. 2-Wire Serial Interface Timing Diagram
B Version
, unless otherwise noted.
6
7
8
0.3
Typ
0.7
12
t
6
t
2
2
Max
8
9
10
Rev. B | Page 5 of 24
Conditions/Comments
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
May be CMOS driven
t
t
Capacitive load for each bus line
HIGH
LOW
HD,STA
SU,DAT,
HD,DAT
SU,STA
SU,STO
BUF
R
F
F
, rise time of both SCL and SDA when receiving
, fall time of SDA when receiving
, fall time of both SCL and SDA when transmitting
, bus free time between a stop condition and a start condition
, SCL low time
, SCL high time
, setup time for repeated start
, start/repeated start condition hold time
, stop condition setup time
t
, data hold time
data setup time
11
Unit
μs
μs
μs
nV-s
V/μs
nV-s
t
5
IH MIN
Conditions/Comments
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
V
1 LSB change around major carry
DD
of the SCL signal) in order to bridge the undefined region of SCL’s
MIN
= 5 V
t
7
CONDITION
REPEATED
to T
START
MAX
, unless otherwise noted.
t
4
4
AD5301/AD5311/AD5321
t
1
4
4
CONDITION
STOP
t
8