AD9750 Analog Devices, AD9750 Datasheet
AD9750
Specifications of AD9750
Available stocks
Related parts for AD9750
AD9750 Summary of contents
Page 1
... The AD9750 is available in 28-lead SOIC and TSSOP packages specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9750 is a member of the wideband TxDAC high per- formance product family that provides an upward or downward component selection path based on resolution ( bits), performance and cost ...
Page 2
... AD9750–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT ...
Page 3
... Measured single ended into 50 load. Specifications subject to change without notice. REV AVDD = +5 V, DVDD = + MIN MAX OUTFS 50 Doubly Terminated, unless otherwise noted) Min ) 125 –3– AD9750 = 20 mA, Differential Transformer Coupled Output, Typ Max 2.5 2 ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9750 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... NC DB5 5 24 AVDD AD9750 DB4 6 23 ICOMP TOP VIEW (Not to Scale) DB3 7 22 IOUTA DB2 8 21 IOUTB 9 20 DB1 ACOM DB0 ADJ REFIO 13 16 REFLO SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9750 ...
Page 6
... T . For MIN MAX +5V REFLO AVDD ACOM 150pF AD9750 PMOS ICOMP CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB FOR DB9–DB1 SWITCH LATCHES ...
Page 7
... A – dBc OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9750 = +25 C, SFDR up to Nyquist, unless otherwise noted 0dBF –6dBF S 60 –12dBF – MHz OUT Figure 5 ...
Page 8
... AD9750 0.2 0.15 0.1 0.05 0 –0.05 –0.1 1000 0 200 400 600 800 CODE Figure 12. Typical INL 125MSPS CLOCK – 13.5MHz OUT1 f = 14.5MHz OUT2 –20 AMPLITUDE = 0dBF S SDFR = 75dBc –30 –40 –50 –60 –70 –80 –90 –100 – MHz OUT Figure 15 ...
Page 9
... FUNCTIONAL DESCRIPTION Figure 17 shows a simplified block diagram of the AD9750. The AD9750 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
Page 10
... Figure 19. External Reference Configuration AVDD 1.2V AD1580 REFERENCE CONTROL AMPLIFIER The AD9750 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I The control amplifier is configured as a V-I converter as shown in Figure 19, such that its current output, I the ratio of the V in Equation 4 ...
Page 11
... The negative output compliance range of –1 set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9750. The positive output compliance range is slightly dependent on the full-scale output current, I ...
Page 12
... The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9750 as well as its required min/ max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise ...
Page 13
... Figure 27. I APPLYING THE AD9750 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9750. Unless otherwise noted assumed that I OUTFS ing the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration ...
Page 14
... In this case, AVDD which is the positive analog supply for both the AD9750 and the op amp is also used to level-shift the differ- ential output of the AD9750 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
Page 15
... PSRR of the DAC at 1 MHz, which Figure 33 becomes Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9750 fea- tures separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system ...
Page 16
... Analog Devices’ application notes AN-280 and AN-333. APPLICATIONS Using the AD9750 for Quadrature Amplitude Modulation (QAM) QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in FDM as well as spreadspectrum (i ...
Page 17
... AD9750 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9750 in various configurations. Possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs ...
Page 18
... AD9750 Figure 38. Evaluation Board Schematic –18– REV. 0 ...
Page 19
... REV. 0 Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) –19– AD9750 ...
Page 20
... AD9750 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) –20– REV. 0 ...
Page 21
... REV. 0 Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom –21– AD9750 ...
Page 22
... AD9750 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60 ...