AD7396 Analog Devices, AD7396 Datasheet
AD7396
Specifications of AD7396
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AD7396 Summary of contents
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... Both parts are offered in the same pinout, allowing users to select the amount of resolution appropriate for their applications without circuit card changes. The AD7396/AD7397 are specified for operation over the ex- tended industrial (– +85 C) temperature range. The AD7397AR is specified for the – +125 C automotive temperature range ...
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... SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Shutdown Supply Current Power Dissipation Power Supply Sensitivity NOTES 1 One LSB = V /4096 V for the 12-bit AD7396. REF 2 The first two codes (000 , 001 ) are excluded from the linearity error measurement These parameters are guaranteed by design and not subject to production testing. ...
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... H DNL < 1 LSB Load IL SHDN = Load Load (10 and timed from a voltage level of +1 –3– AD7396/AD7397 < +85 C, unless otherwise noted 10 10% Units 10 10 1.75 1.75 2.0 2 9.0 9 ...
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... AD7396/AD7397 t CSW A D0–D11 LDA, LDB t RSW OUT Figure 2. Timing Diagram CS LDA LDB RS A ^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V exhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = “ ...
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... C to +125 C AD7397ARU 10 – +85 C The AD7396/AD7397 contains 1365 transistors. The die size measures 89 mil CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7396/AD7397 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges ...
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... DD Resets Input and DAC Register to Zero Condition. Asynchronous active low input. Twelve Parallel Input Data Bits. D11 = MSB Pin 18 LSB Pin 7, AD7396. No Connect Pins 7 and 8 On the AD7397 Only. Ten Parallel Input Data Bits MSB Pin 18 LSB Pin 9, AD7397 Only. ...
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... V = +3V AD7396 +2.5V REF T = –55 C 1.0 A 0.5 0.0 –0 + –1.0 –1.5 0 512 1024 1536 2048 2560 3072 3584 4096 CODE – Decimal Figure 4. AD7396 INL vs. Code and Temperature 1 +2.7V AD7397 DD 0 +2.5V REF 0.6 0.4 0.2 0.0 –0 +25 C, +85 C, –55 C –0.4 A SUPERIMPOSED –0.6 –0.8 –1.0 ...
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... AD7396/AD7397 0 –5 – +3V DD –15 CODE = FULL SCALE –20 –25 –30 –35 –40 –45 –50 100 1k 10k 100k 1M FREQUENCY – Hz Figure 13. Reference Multiplying Gain vs. Frequency 5 + 4.5 4.0 3.5 V FROM LOGIC LOW TO HIGH 3.0 2.5 2.0 V FROM LOGIC HIGH TO LOW 1.5 1 – Figure 16. Logic Threshold Voltage vs ...
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... V OUT Using Equation 2, the nominal midscale voltage at V 1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step size is = 2.5 For the 12-bit AD7396 operating from a 5.0 V reference equa- tion [1] becomes: V OUT Using Equation 3, the AD7396 provides a nominal midscale voltage of 2.50 V for D = 2048, and a full-scale output of 4 ...
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... AD7396/AD7397 power supply. If this mode of interface is used, make sure that the V of the 5 V CMOS meets the V OL ment of the AD7396/AD7397 operating See Figure 16 for a graph for digital logic input threshold versus operating V supply voltage ...
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... SHDN pin to the V voltage thereby disabling this DD function. UNIPOLAR OUTPUT OPERATION This is the basic mode of operation for the AD7396. As shown in Figure 29, the AD7396 has been designed to drive loads as low parallel with 100 pF. The code table for this operation is shown in Table II. +2.7V TO +5. ...
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... AD7396/AD7397 I < 262 A SY +5V 470k 470k 200 A V REF DD OP196 V AD7397 C OUTA GND ONLY ONE CHANNEL SHOWN. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY. Figure 30. Bipolar Output Operation 24-Lead SOIC Package (R-24) 0.6141 (15.60) 0.5985 (15.20 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) 0.0118 (0.30) SEATING (1 ...