AD9761 Analog Devices, AD9761 Datasheet
AD9761
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AD9761 Summary of contents
Page 1
... The AD9761 is manufactured on an advanced low cost CMOS process. It operates from a single supply 5.5 V and consumes 200 mW of power. To make the AD9761 complete, it also offers an internal 1.20 V temperature-compensated band gap reference. REV. C Information furnished by Analog Devices is believed to be accurate and reliable ...
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... AD9761–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION DC ACCURACY 1 Integral Nonlinearity Error (INL 25° MIN MAX Differential Nonlinearity (DNL 25° MIN MAX Monotonicity (10-Bit) ANALOG OUTPUT Offset Error Offset Matching between DACs Gain Error (without Internal Reference) ...
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... REFER TO DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATION SECTION. t CINV Figure 1.Timing Diagram –3– mA, Differential Transformer Coupled Output, Max Unit MSPS ns Input Clock Cycles pV Bits –58 dB – dBc = 10 mA unless otherwise noted.) Max Unit V V 1.3 V 0.9 V +10 µA +10 µ AD9761 ...
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... AD9761 DIGITAL FILTER SPECIFICATIONS Parameter MAXIMUM INPUT CLOCK RATE (f DIGITAL FILTER CHARACTERISTICS 1 Pass Bandwidth : 0.005 dB Pass Bandwidth: 0.01 dB Pass Bandwidth: 0.1 dB Pass Bandwidth: –3 dB Linear Phase (FIR Implementation) Stop-Band Rejection: 0 0.7 f CLOCK 2 Group Delay 3 Impulse Response Duration –40 dB –60 dB NOTES 1 Excludes SINx/x characteristic of DAC. ...
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... CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9761 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... SLEEP Mode Operation section. PIN CONFIGURATION (MSB) DB9 1 28 RESET/SLEEP DB8 2 27 COMP1 DB7 3 26 IOUTA DB6 4 25 IOUTB 5 24 ACOM DB5 AD9761 DB4 6 AVDD 23 TOP VIEW (Not to Scale) DB3 7 22 COMP2 DB2 8 21 FSADJ DB1 9 20 REFIO (LSB) DB0 10 19 ...
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... DAC, relative to a full-scale signal applied at the DAC input within the pass band. Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. Impulse Response Response of the device to an impulse applied to the input. –7– AD9761 N = (SINAD – 1.76)/6.02 ...
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... AD9761—Typical Performance Characteristics Typical AC Characterization Curves @ 5 V Supplies (AVDD = 5 V, DVDD = Doubly Terminated Load, T performance shown.) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START: 0Hz STOP: 40MHz TPC 1. Single-Tone SFDR ( DATA CLOCK ...
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... SFDR @ 2.5mA 65 SINAD @ 5mA SINAD @ 10mA SINAD @ 2.5mA (MHz) OUT TPC 17. SINAD/SFDR vs. I OUTFS ( /2, Single-Ended Output) DATA –9– AD9761 85 DIFF –6dBFS 80 S/E –6dBFS 75 70 DIFF 0dBFS 65 S/E 0dBFS 60 0 0.5 1.0 1.5 2.0 2.5 f (MHz) OUT TPC 12. SFDR vs /2) ...
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... CONTROL SELECT INPUT Figure 4. Dual DAC Functional Block Diagram Referring to Figure 4, the AD9761 consists of an analog sec- tion and a digital section. The analog section includes matched I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and a reference control amplifier.The digital section includes two 2 ...
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... Figures 2a and 2b. Table I lists the idealized filter coefficients that correspond to the filter’s impulse response. The digital section of the AD9761 also includes an input interface section designed to support interleaved I and Q input data from a single 10-bit bus. This section de-interleaves the I and Q input data while ensuring its proper pairing for the 2 ...
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... REFIO is copied REF Figure 9 shows an equivalent circuit of the AD9761’s I (or Q) DAC output. It consists of a parallel array of PMOS current sources in which each current source is switched to either IOUTA or IOUTB via a differential PMOS switch result, between ...
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... Digital Interface An example helps illustrate the digital timing and control requirements to ensure proper pairing of I and Q data. In this example, the AD9761 is assumed to interface with a host processor on a dedicated data bus and the state machine is reset by asserting a Logic Level 1 to the RESET/SLEEP input for a duration of one clock cycle ...
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... The power-up and power-down characteristics of the AD9761 are dependent upon the value of the compensation capacitor connected to COMP1 and COMP3. With a nominal value of 0.1 µF, the AD9761 takes less than 5 µs to power down and approximately 3. power back up. POWER DISSIPATION The power dissipation of the AD9761 is dependent on several ...
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... Ratio @ DVDD = 3 V DVDD APPLYING THE AD9761 Output Configurations The following sections illustrate some typical output configu- rations for the AD9761. Unless otherwise noted assumed that I is set to a nominal 10 mA. For applications requir- OUTFS ing the optimum dynamic performance, a differential output configuration is suggested ...
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... The differential circuit shown in Figure 19 provides the neces- sary level-shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9761 and the op amp, is also used to level-shift the differ- ential output of the AD9761 to midsupply (i.e., AVDD/2). AD9761 200 ...
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... Separate 50 terminated SMA connectors are also provided for the CLOCK, WRITE, and SELECT inputs. Provisions are also made to operate the AD9761 with either the internal or an external reference as well as to exercise the power-down feature. ...
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... AD9761 Figure 24a. Evaluation Board Schematic –18– REV. C ...
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... REV. C Figure 24b. Evaluation Board Schematic –19– AD9761 ...
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... AD9761 Figure 25. Silkscreen Layer—Top Figure 26. Component Side PCB Layout (Layer 1) –20– REV. C ...
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... REV. C Figure 27. Ground Plane PCB Layout (Layer 2) Figure 28. Power Plane PCB Layout (Layer 3) –21– AD9761 ...
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... AD9761 Figure 29. Solder Side PCB Layout (Layer 4) Figure 30. Silkscreen Layer—Bottom –22– REV. C ...
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... MAX 0.05 MIN REV. C OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 0.09 0.65 0.38 BSC 0.22 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-150AH –23– AD9761 8 0.95 4 0.75 0 0.55 ...
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... AD9761 Revision History Location 6/03—Data Sheet changed from REV REV. C. Renumbered TPCs and subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Changes to Figure Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 –24– Page REV. C ...