AD9761 Analog Devices, AD9761 Datasheet - Page 16

• Manufacturer Part Number: AD9761
• Description: 10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9761

• Resolution (bits): 10bit
• Dac Update Rate: 40MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

The differential circuit shown in Figure 19 provides the neces-
sary level-shifting required in a single-supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9761 and the op amp, is also used to level-shift the differ-
ential output of the AD9761 to midsupply (i.e., AVDD/2).
Single-Ended Unbuffered Voltage Output
Figure 20 shows the AD9761 configured to provide a uni-
polar output range of approximately 0 V to 0.5 V since the
nominal full-scale current, I
R
filter, R
IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
Different values of I
as the positive compliance range is adhered to.
Differential, DC-Coupled Output Configuration with
Level Shifting
Some applications may require the AD9761 differential outputs
to interface to a single-supply quadrature upconverter.
Although most of these devices provide differential inputs,
its common-mode voltage range does not typically extend
to ground. As a result, the ground-referenced output signals
shown in Figure 20 must be level shifted to within the
specified common-mode range of the single-supply quadrature
upconverter. Figure 21 shows the addition of a resistor pull-up
network that provides the level shifting function. The use
of matched resistor networks will maintain maximum gain
matching and minimum offset performance between the
I and Q channels. Note, the resistor pull-up network will
introduce approximately 6 dB of signal attenuation.
AD9761
LOAD
Figure 20. 0 V to 0.5 V Unbuffered Voltage Output
Figure 19. Single-Supply DC Differential Coupled
Circuit
of 50 . In the case of a doubly terminated low-pass
LOAD
AD9761
represents the equivalent load resistance seen by
IOUTA
IOUTB
AD9761
OUTFS
IOUTB
IOUTA
R
LOAD
50
and R
C
I
OUTFS
OUTFS
OPT
LOAD
= 10mA
R
50
, of 10 mA flows through an
200
200
LOAD
50
can be selected as long
1k
V
0V TO 0.5V
50
OUT
AD8042
500
=
1k
AVDD
LOAD
.
–16–
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of
the printed circuit board design is often as important as the
circuit design. Proper RF techniques must be used in device
selection, placement and routing, and supply bypassing and
grounding. The evaluation board for the AD9761, which
uses a 4-layer PC board, serves as a good example for the
previously mentioned considerations. The evaluation board
provides an illustration of the recommended printed circuit
board ground, power, and signal plane layout.
Proper grounding and decoupling should be a primary objec-
tive in any high speed, high resolution system. The AD9761
features separate analog and digital supply and ground pins
to optimize the management of analog and digital ground
currents in a system. In general, AVDD, the analog supply,
should be decoupled to ACOM, the analog common, as
close to the chip as physically possible. Similarly, DVDD,
the digital supply should be decoupled as close to DCOM as
physically as possible.
For those applications requiring a single 5 V or 3.3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 22.
The circuit consists of a differential LC filter with separate
power supply and return lines. Lower noise can be attained
using low ESR type electrolytic and tantalum capacitors.
Figure 22. Differential LC Filter for Single 5 V or 3 V
Applications
TTL/CMOS
CIRCUITS
LOGIC
Figure 21. Differential, DC-Coupled Output
Configuration with Level-Shifting
5V OR 3V POWER
AD9761
SUPPLY
IOUTB
IOUTA
FERRITE
BEADS
**OHMTEK TO MC-1603-1000D
*OHMTEK TO MC-1603-5000D
500*
500*
50**
+
–
AVDD
100F
ELECT.
50**
500*
500*
–
+
10F–22F
TANT.
V
V
IN+
IN–
UPCONVERTER
QUADRATURE
0.1F
CER.
AVDD
ACOM
REV. C