AD7390 Analog Devices, AD7390 Datasheet - Page 9

• Manufacturer Part Number: AD7390
• Description: +3/+5 Volt Serial-Input Micropower 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7390

• Resolution (bits): 12bit
• Dac Update Rate: 17kSPS
• Dac Settling Time: 60µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

The AD7390 should be powered directly from the system
power supply. This arrangement, shown in Figure 6, employs an
LC filter and separate power and ground connections to isolate
the analog section from the logic switching transients.
Whether or not a separate power supply trace is available, how-
ever, generous supply bypassing will reduce supply-line induced
errors. Local supply bypassing consisting of a 10 µF tantalum
electrolytic in parallel with a 0.1 µF ceramic capacitor is recom-
mended in all applications (Figure 7).
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure (Figure 8) that allows logic input voltages to exceed the
V
one or more of the digital inputs with a 5 V CMOS logic input-
voltage level while operating the AD7390/AD7391 on a 3 V power
supply. If this mode of interface is used, make sure that the V
of the 5 V CMOS meets the V
AD7391 operating at 3 V. See TPC 6 for a graph for digital
logic input threshold versus operating V
In order to minimize power dissipation from input-logic levels that
are near the V
Schmitt trigger design was used that minimizes the input-buffer
current consumption compared to traditional CMOS input
stages. TPC 5 shows a plot of incremental input voltage versus
DD
TTL/CMOS
CIRCUITS
LOGIC
supply voltage. This feature can be useful if the user is driving
POWER SUPPLY
CLR
CLK
5V
SDI
LD
IH
FERRITE BEAD:
TWO TURNS, FAIR-RITE
#2677006301
and V
OPTIONAL EXTERNAL
REFERENCE BYPASS
LOGIC
C
GND
1
2
3
4
V
DD
IN
IL
REF
AD7390
AD7391
logic input voltage specifications, a
2.7V TO 5.5V
8
GND
OR
V
5
DD
IL
7
input requirement of the AD7390/
100 F
ELECT.
6
0.1 F
DD
10 F–22 F
TANTALUM
supply voltage.
10 F
V
OUT
0.1 F
CERAMIC
CAPACITOR
5V
5V
RETURN
OL
supply current showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions. A
secondary advantage of this Schmitt trigger is the prevention of
false triggers that would occur with slow moving logic transi-
tions when a standard CMOS logic interface or opto isolators
are used. The logic inputs SDI, CLK, LD, CLR all contain the
Schmitt trigger circuits.
DIGITAL INTERFACE
The AD7390/AD7391 have a double-buffered serial data input.
The serial-input register is separate from the DAC register,
which allows preloading of a new data value into the serial regis-
ter without disturbing the present DAC values. A functional
block diagram of the digital section is shown in Figure 4, while
Table I contains the truth table for the control logic inputs.
Three pins control the serial data input. Data at the Serial Data
Input (SDI) is clocked into the shift register on the rising edge
of CLK. Data is entered in MSB-first format. Twelve clock
pulses are required to load the 12-bit AD7390 DAC value. If
additional bits are clocked into the shift register, for example
when a microcontroller sends two 8-bit bytes, the MSBs are
ignored (Figure 9). The CLK pin is only enabled when Load
(LD) is high. The lower resolution 10-bit AD7391 contains a
10-bit shift register. The AD7391 is also loaded MSB first with
10 bits of data. Again if additional bits are clocked into the shift
register, only the last 10 bits clocked in are used.
The Load pin (LD) controls the flow of data from the shift
register to the DAC register. After a new value is clocked into
the serial-input register, it will be transferred to the DAC register
by the negative transition of the Load pin (LD).
RESET (CLR) PIN
Forcing the CLR pin low will set the DAC register to all zeros
and the DAC output voltage will be zero volts. The reset function
is useful for setting the DAC outputs to zero at power-up or
after a power supply interruption. Test systems and motor
controllers are two of many applications which benefit from
powering up to a known state. The external reset pulse can be
generated by the microprocessor’s power-on RESET signal, by
an output from the microprocessor, or by an external resistor
and capacitor. CLR has a Schmitt trigger input which results in
a clean reset function when using external resistor/capacitor
generated pulses. The CLR input overrides other logic inputs,
specifically LD. However, LD should be set high before CLR
goes high. If CLR is kept low, then the contents of the shift
register will be transferred to the DAC register as soon as CLR
returns high. See the Control-Logic Truth Table I.
MSB
D11–D0: 12-BIT AD7390 DAC VALUE; D9–D0: 10-BIT AD7391 DAC VALUE
X = DON’T CARE
THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC
B15 B14 B13 B12 B11 B10 B9 B8 B7
X
X
X
X
X
X
BYTE 1
X
X
D11 D10 D9 D8 D7
X
X
D9 D8 D7
LSB MSB
AD7390/AD7391
B6
D6
D6
B5
D5
D5
B4
D4
D4
BYTE 0
B3
D3
D3
B2
D2
D2
B1
D1
D1
LSB
B0
D0
D0