AD7835 Analog Devices, AD7835 Datasheet
AD7835
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AD7835 Summary of contents
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... V of the DSG potential. As the supplies stabilize, the DAC output levels move to the exact DSG potential (assuming CLR is exercised). The AD7834 is available in a 28-lead 0.3" SOIC package and a 28-lead 0.6" PDIP package, and the AD7835 is available in a 44-lead MQFP package and a 44-lead PLCC package. FUNCTIONAL BLOCK DIAGRAMS (–) V ...
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... Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14 DAC Architecture....................................................................... 14 Data Loading—AD7834 Serial Input Device ......................... 14 Data Loading—AD7835 Parallel Loading Device ................. 14 Unipolar Configuration............................................................. 15 Bipolar Configuration................................................................ 16 Controlled Power-On of the Output Stage.................................. 17 REVISION HISTORY 8/07—Rev Rev. D Changes to Table 5 ........................................................................... 7 Added Table 6 ...
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... DSG ±5% for specified performance. ±5% for specified performance. ±5% for specified performance DGND. INH CC INL AD7834 2.4 V min 0.8 V max. INH INL AD7835 2.4 V min 0.8 V max. INH INL AD7834: outputs unloaded. AD7835: outputs unloaded. Outputs unloaded. ...
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... DSG ±5% for specified performance. ±5% for specified performance. ±5% for specified performance DGND. INH CC INL AD7834 2.4 V min 0.8 V max. INH INL AD7835 2.4 V min 0.8 V max. INH INL AD7834: outputs unloaded. AD7835: outputs unloaded. Outputs unloaded. ...
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... Measured with V alternately loaded with all 0s and all 1s. 0.5 0.5 0.5 Ω See the Terminology section. 100 100 100 dB See the Terminology section; applies to the AD7835 only nV-s See the Terminology section nV-s Feedthrough to DAC output under test due to change in digital input code to another converter. ...
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... Data setup time Data hold time LDAC to CS setup time CS to LDAC setup time LDAC to CS hold time LDAC, CLR pulse width BYSHF LDAC UPDATE LDAC UPDATE) Figure 4. AD7835 Timing Diagram ...
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... V DD Package Type PDIP SOIC MQFP PLCC − T )/θ ESD CAUTION Rev Page AD7834/AD7835 must not exceed V by more than IN4148 SD103C AD7834/ AD7835 Figure 5. Diode Protection θ Unit JA 75 °C/W 75 °C/W 95 °C/W 55 °C/W ...
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... AD7834/AD7835 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 7. AD7834 Pin Function Descriptions Pin No. Pin Mnemonic DSG 3 V (−) REF 4 V (+) REF 5, 24, 25, 26 22 OUT OUT 8 DGND SCLK 11 DIN 12,13,14,15,16 PA0 to PA4 17 PAEN 18 FSYNC 19 LDAC ...
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... A2 12 TOP VIEW (Not to Scale CLR 15 LDAC 16 BYSHF Figure 8. AD7835 PLCC Pin Configuration 1 and V 2 are forced to the OUT OUT 3 and V 4 follow DSGB). When CLR is brought high, the OUT OUT DSGB 37 V ...
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... REF Description Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the bottom eight data inputs, DB0 to DB7, are used for data loading, and the top six data inputs, DB8 to DB13, should be hardwired to a logic low ...
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... V (+) (V) REF Figure 11. Typical INL vs. V (+), V REF (−) = −6 V REF Rev Page AD7834/AD7835 0.50 0.45 DAC 1 0.40 0.35 DAC 3 DAC 4 0.30 0.25 DAC 2 0.20 0.15 0.10 0.05 TEMP = 25°C ALL DACs FROM 1 DEVICE 0 0 2.5 5.0 V (+) (V) REF Figure 12. Typical INL vs. V (+), V (+) – V REF REF 0 ...
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... AD7834/AD7835 0.7 VERT = 100mV/DIV HORIZ = 1μs/DIV 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 Figure 15. Typical Digital/Analog Glitch Impulse 8 VERT = 2V/DIV HORIZ = 1.2μs/DIV (+) = +7V REF 2 V (–) = –3V REF 0 –2 VERT = 25mV/DIV HORIZ = 2.5μs/DIV –4 Figure 16. Settling Time(+) (+) = +7V REF 2 V (–) = –3V ...
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... DAC expressed in decibels (dB). The AD7834 has no specification for channel-to-channel isolation because it has one reference for all DACs. Channel-to-channel isolation is specified for the AD7835. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and the subsequent analog output (O/P) change at another converter ...
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... DATA LOADING—AD7835 PARALLEL LOADING DEVICE Data is loaded into the AD7835 in either straight 14-bit wide words or in two 8-bit bytes. In systems that transfer 14-bit wide data, the BYSHF input should be hardwired to V straight 14-bit parallel-loading DAC. ...
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... To adjust offset, disconnect the V load the DAC with all 0s, and adjust the V until V • To adjust gain, load the AD7834/AD7835 with all 1s and adjust R1 until V Many circuits do not require these offset and gain adjustments. In these circuits, R1 can be omitted. Pin 5 of the AD586 can be left open circuit, and Pin 2 (V tied ...
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... AD588 provides precision ±5 V tracking outputs that are fed to the V (+) and V (−) inputs of the AD7834/AD7835. REF REF The code table for bipolar operation of the AD7834/AD7835 is shown in Table 13. Table 13. Code Table for Bipolar Operation Binary Number in DAC Latch MSB LSB Analog Output (V ...
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... CONTROLLED POWER-ON OF THE OUTPUT STAGE A block diagram of the output stage of the AD7834/AD7835 is shown in Figure 21 capable of driving a load of 10 kΩ in parallel with 200 pF are transmission gates used control the power-on voltage present at V used in conjunction with the CLR input to set V defined voltage present at the DSG pin ...
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... Thus, for specified operations, the maximum voltage applied to the DSG pin increases to the maximum allowable V DSG is the minimum V AD7835 has fully powered on, the outputs can track any DSG voltage within this minimum/maximum range. Rev Page (+) voltage, and the minimum voltage applied to REF (− ...
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... POWER-ON OF THE AD7834/AD7835 Power is normally applied to the AD7834/AD7835 in the following sequence: first V and V , then (+) and V (−). The V pins are not allowed to float when REF REF REF power is applied to the part. V (+) is not allowed to go below REF V (−) − 0 (−) is not allowed to go below V ...
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... Therefore, the user has to ensure that data in the SBUF register is arranged correctly so the data is received MSB first by the AD7834/AD7835. When data trans- mitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 80C51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the trans- mit cycle ...
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... AD7835 interfaced to a generic 16-bit microcontroller/DSP processor. address lines from the processor are connected to A0, A1, and A2 on the AD7835 as shown. The upper address lines are decoded to provide a chip select signal for the AD7835. They are also decoded, in conjunction with the lower address lines if ...
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... Figure 32 shows an 8-bit interface between the AD7835 and a generic 8-bit microcontroller/DSP processor. Pin D13 to Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the processor are connected to Pin D7 to Pin D0 of the AD7835. BYSHF is driven by the A0 line of the processor. This maps the DAC upper bits and lower bits into adjacent bytes in the proces- sor address space ...
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... However, the output of the pin driver varies from − with respect to DUT GND as the DAC input code varies from 000 . . . 000 to 111 . . . 111. The V the DSGA pin. When a clear is performed on the AD7835, the output of the pin driver with respect to DUT GND. Rev Page AD7834/AD7835 PAEN line doesn’ ...
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... DUT they couple noise onto the die. The analog ground plane can run GND under the AD7834/AD7835 to avoid noise coupling. The power supply lines of the AD7834/AD7835 can use as large a trace as DUT GND possible to provide low impedance paths and reduce the effects of glitches on the power supply line ...
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... PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) Rev Page AD7834/AD7835 45° 8° 0° 1.27 (0.0500) 0.33 (0.0130) 0.40 (0.0157) 0.20 (0.0079) ...
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... AD7834/AD7835 0.048 (1.22) 0.042 (1.07) 6 0.048 (1.22) 7 PIN 1 0.042 (1.07) IDENTIFIER TOP VIEW (PINS DOWN 0.656 (16.66) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) 2.20 2.00 1.80 0.25 MIN 0.10 COPLANARITY VIEW A ROTATED 90° CCW 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.020 (0.51) 0.042 (1.07) MIN 40 39 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.032 (0.81) 0.026 (0.66 0.045 (1.14) 0.025 (0.64) 0.120 (3.05) SQ 0.090 (2.29) SQ COMPLIANT TO JEDEC STANDARDS MO-047-AC CONTROLLING DIMENSIONS ARE IN INCHES ...
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... AD7835APZ −40°C to +85°C 1 AD7835APZ-REEL −40°C to +85°C AD7835AS −40°C to +85°C AD7835AS-REEL −40°C to +85°C 1 AD7835ASZ −40°C to +85°C 1 AD7835ASZ-REEL −40°C to +85° RoHS Compliant Part. Linearity Error (LSBs) DNL (LSBs) ±2 ±0.9 ± ...
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... AD7834/AD7835 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01006-0-8/07(D) Rev Page ...