AD760 Analog Devices, AD760 Datasheet - Page 11

• Manufacturer Part Number: AD760
• Description: 16/18-Bit Self-Calibrating Serial/Byte DACPORT
• Manufacturer: Analog Devices

Specifications of AD760

• Resolution (bits): 18bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Ser

REV. A
The HC11 generates the requisite 8 clock pulses with data valid
on the rising edges. After the most significant byte is transmit-
ted, the least significant byte (LSBY) is loaded from memory
and transmitted in a similar fashion. To complete the transfer,
the LDAC pin is driven high latching the complete 16-bit word
into the AD760.
I
NEXTPT LDAA
SENDAT LDY
WAIT1
WAIT2
AD760 TO MICROWIRE INTERFACE
The flexible serial interface of the AD760 is also compatible
with the National Semiconductor MICROWIRE* interface.
The MICROWIRE* interface is used on microcontrollers such
as the COP400 and COP800 series of processors. A generic in-
terface to the MICROWIRE interface is shown in Figure 12.
The G1, SK, and SO pins of the MICROWIRE interface are re-
spectively connected to the LDAC, CS and S
AD760.
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 153 µV
(–96 dB). Therefore, the noise must remain below this level in
*MICROWIRE is a registered trademark of National Semiconductor.
NIT
Figure 11. AD760 to 68HC11 (SPI) Interface
Figure 12. AD760 to MICROWIRE Interface
LDAA
STAA
LDAA
STAA
LDAA
STAA
BSR
JMP
BCLR
STAA
LDAA
BPL
LDAA
STAA
LDAA
BPL
BSET
RTS
MICROWIRE
68HC11
#$2F
PORTD
#$38
DDRD
#$50
SPCR
MSBY
SENDAT ;JUMP TO DAC OUTPUT ROUTINE
NEXTPT ;INFINITE LOOP
#$1000
$08,Y,$20 ;DRIVE SS (LDAC) LOW
SPDR
SPSR
WAIT1
LSBY
SPDR
SPSR
WAIT2
$08,Y,$20 ;DRIV SS HIGH TO LATCH DATA
MOSI
SCK
SS
SO
SK
G1
;SS = 1; SCK = 0; MOSI = I
;SEND TO SPI OUTPUTS
;SS, SCK,MOSI = OUTPUTS
;SEND DATA DIRECTION INFO
;DABL INTRPTS,SPI IS MASTER & ON
;CPOL=0, CPHA=0,1MHZ BAUD RATE
;LOAD ACCUM W/UPPER 8 BITS
;POINT AT ON-CHIP REGISTERS
;SEND MS-BYTE TO SPI DATA REG
;CHECK STATUE OF SPIE
;POLL FOR END OF X-MISSION
;GET LOW 8 BITS FROM MEMORY
;SEND LS-BYTE TO SPI DATA REG
;CHECK STATUS OF SPIE
;POLL FOR END OF X-MISSION
S
CS
LDAC
SER
S
LDAC
SER
IN
CS
IN
AD760
AD760
IN
pins of the
–11–
the frequency range of interest. The AD760’s noise spectral
density is shown in Figures 13 and 14. Figure 13 shows the
DAC output noise voltage spectral density for a 20 V span ex-
cluding the reference. This figure shows the l/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/ Hz.
Figure 14 shows the reference wideband noise to be below
125 nV/ Hz.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 µA current through a 0.5 trace will develop a voltage
drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes should also be used, with a single in-
terconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
Figure 13. DAC Output Noise Voltage Spectral Density
Figure 14. Reference Noise Voltage Spectral Density
1000
1000
100
100
10
10
1
1
1
1
10
10
100
100
FREQUENCY – Hz
FREQUENCY – Hz
1k
1k
10k
10k
100k
100k
1M
1M
AD760
10M
10M