DAC8420 Analog Devices, DAC8420 Datasheet - Page 8

• Manufacturer Part Number: DAC8420
• Description: Quad 12-Bit Serial Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of DAC8420

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +15.75V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser

DAC8420
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
4
5
7, 6, 3, 2
8
9
10
11
12
13
14
15
16
VREFLO
Mnemonic
VDD
VREFLO
VREFHI
VOUTA through VOUTD
VSS
GND
SDI
CLK
CS
NC
LD
CLR
CLSEL
VREFHI
VOUTD
VOUTC
VOUTB
VOUTA
VDD
VSS
Figure 4. PDIP and CERDIP
1
2
3
4
5
6
7
8
NC = NO CONNECT
(Not to Scale)
DAC8420
TOP VIEW
16
15
14
13
12
10
11
9
CLSEL
CLR
LD
NC
CS
CLK
SDI
GND
Description
Positive Power Supply, 5 V to 15 V.
Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable
range is V
Reference Input. Upper DAC ladder reference voltage input. Allowable range is (V
(V
Buffered DAC Analog Voltage Outputs.
Negative Power Supply, 0 V to −15 V.
Power Supply, Digital Ground.
Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register,
which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI
is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8.
System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed
with CS.
Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and
disables the serial data register input when high. When low, data input clocking is enabled (see
Table 6). CS is CMOS/TTL compatible.
No Connect = Don’t Care.
Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained
in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD,
independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible.
Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to
zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is
unaffected by this control. CLR is CMOS/TTL compatible.
Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A
through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS/
TTL compatible.
VREFLO
+ 2.5 V).
SS
to (V
VREFHI
Rev. B | Page 8 of 24
− 2.5 V).
VREFLO
VREFHI
VOUTD
VOUTC
VOUTB
VOUTA
VDD
VSS
1
2
3
4
5
6
7
8
NC = NO CONNECT
Figure 5. SOIC
(Not to Scale)
DAC8420
TOP VIEW
16
15
14
13
12
10
11
9
CLSEL
CLR
LD
NC
CS
CLK
SDI
GND
DD
− 2.5 V) to