AD7249 Analog Devices, AD7249 Datasheet - Page 2

• Manufacturer Part Number: AD7249
• Description: LC2MOS Dual 12-Bit Serial DACPORT
• Manufacturer: Analog Devices

Specifications of AD7249

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser

+5 V, R
Parameter
STATIC PERFORMANCE
REFERENCE OUTPUT
REFERENCE INPUT
DIGITAL INPUTS
ANALOG OUTPUTS
AC CHARACTERISTICS
POWER REQUIREMENTS
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
AD7249–SPECIFICATIONS
Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%.
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
See Terminology.
Measured with respect to REFIN and includes unipolar/bipolar offset error.
Guaranteed by design not production tested.
0 V to 10 V output range available only with V
Resolution
Relative Accuracy
Differential Nonlinearity
Unipolar Offset Error
Bipolar Zero Error
Full-Scale Error
Full-Scale Temperature Coefficient
REFOUT
Reference Temperature Coefficient
Reference Load Change
(∆V
Reference Input Range, REFIN
Input Current
Input High Voltage, V
Input Low Voltage, V
Input Current
Input Capacitance
Output Range Resistor,
Output Voltage Ranges
Output Voltage Ranges
DC Output Impedance
Voltage Output Settling-Time
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
V
V
I
I
DD
SS
DD
SS
I
R
Positive Full-Scale Change
Negative Full-Scale Change
(Dual Supplies)
IN
REFOUT
Range (Dual Supplies)
OFSA
L
Range
= 2 k , C
& R
vs. I
OFSB
L
3, 4
)
3
L
3
= 100 pF to AGND. All specifications T
5
3
3
3
INL
INH
6
6
3
5
3
A Version
12
± 1
± 0.9
± 5
± 6
± 6
± 5
4.95/5.05
± 25
–1
4.95/5.05
5
2.4
0.8
± 1
8
15/30
+5, +10
+5, +10, ± 5
10
10
30
10
10
+10.8/+16.5
–10.8/–16.5
15
5
0.5
DD
≥ 14.25 V.
2
B Version
12
± 1/2
± 0.9
± 5
± 5
± 6
± 5
4.95/5.05
± 25
–1
4.95/5.05
5
2.4
0.8
± 1
8
15/30
+5, +10
+5, +10, ± 5
10
10
30
10
10
+11.4/+15.75 +11.4/+15.75 V min/V max
–11.4/–15.75
15
5
0.5
(V
MIN
DD
to T
= +12 V to +15 V,
MAX
2
unless otherwise noted.)
–11.4/–15.75
S Version
12
± 1
± 0.9
± 6
± 7
± 7
± 5
4.95/5.05
± 30
–1
4.95/5.05
5
2.4
0.8
± 1
8
15/30
+5, +10
+5, +10, ± 5
0.5
10
10
30
10
10
15
5
1
V
2
SS
= O V or –12 V to –15 V,
Unit
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
ppm of FSR/°C typ
V min/V max
ppm/°C typ
mV max
V min/V max
µA max
V min
V max
µA max
pF max
kΩ min/ max
V
V
Ω typ
µs max
µs max
nV secs typ
nV secs typ
nV secs typ
V min/V max
mA max
mA max
Test Conditions/Comments
Guaranteed Monotonic
V
Latch Contents All 0s
V
DAC Latch Contents All 0s
Reference Load Current (I
Change (0 µA–100 µA)
5 V ± 1%
V
Single Supply; V
Dual Supply; V
Settling Time to Within
± 1/2 LSB of Final Value
Typically 3 µs
Typically 5 µs
1 LSB Change Around
Major Carry
For Specified Performance Unless
Otherwise Stated
For Specified Performance Unless
Otherwise Stated
Output Unloaded; Typically 11 mA
Output Unloaded; Typically 3 mA
1
SS
SS
IN
AGND = DGND = O V, REFIN =
= 0 V or –12 V to –15 V
= –12 V to –15 V
= 0 V to V
DD
SS
SS
= –12 V or –15 V
= 0 V
1
L
1
)
; DAC