AD7840 Analog Devices, AD7840 Datasheet - Page 4

• Manufacturer Part Number: AD7840
• Description: Complete 14-Bit CMOS DAC
• Manufacturer: Analog Devices

Specifications of AD7840

• Resolution (bits): 14bit
• Dac Update Rate: 400kSPS
• Dac Settling Time: 2.5µs
• Max Pos Supply (v): +5.25V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser

AD7840
DIP
Pin
No.
1
2
3
4
5
6
7–11
12
13–16 D4–D1
17
18
19
20
21
22
23
24
Pin
Mnemonic
CS/SERIAL
WR/SYNC
D13/SDATA
D12/SCLK
D11/FORMAT
D10/JUSTIFY
D9–D5
DGND
D0
V
AGND
V
V
REF OUT
REF IN
LDAC
DD
OUT
SS
Function
Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used
in conjunction with WR to load parallel data to the input latch. For applications where CS is perma-
nently low, an R, C is required for correct power-up (see LDAC input). If this input is tied to V
fines the AD7840 for serial mode operation.
Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with CS to load
parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with se-
rial data expected after the falling edge of this signal.
Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode,
SDATA is the serial data input which is used in conjunction with SYNC and SCLK to transfer serial data
to the AD7840 input latch.
Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is
the serial clock input. Serial data bits are latched on the falling edge of SCLK when SYNC is low.
Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic
1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates
that the LSB is the first valid bit (see Table I).
Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode,
this input controls the serial data justification (see Table I).
Data Bit 9 to Data Bit 5. Parallel data inputs.
Digital Ground. Ground reference for digital circuitry.
Data Bit 4 to Data Bit 1. Parallel data inputs.
Data Bit 0 (LSB). Parallel data input.
Positive Supply, +5 V
Analog Ground. Ground reference for DAC, reference and output buffer amplifier.
Analog Output Voltage. This is the buffer amplifier output voltage. Bipolar output range ( 3 V with REF
IN = +3 V).
Negative Supply Voltage, –5 V
Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To operate the
AD7840 with internal reference, REF OUT should be connected to REF IN. The external load capability
of the reference is 500 A.
Voltage Reference Input. The reference voltage for the DAC is applied to this pin. It is internally buffered
before being applied to the DAC. The nominal reference voltage for correct operation of the AD7840 is
3 V.
Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling
edge of this signal (see Interface Logic Information section). The AD7840 should be powered-up with
LDAC high. For applications where LDAC is permanently low, an R, C is required for correct power-up
(see Figure 19).
PIN FUNCTION DESCRIPTION
5%.
Table I. Serial Data Modes
5%.
–4–
SS
, it de-
REV. B