AD664 Analog Devices, AD664 Datasheet - Page 11

• Manufacturer Part Number: AD664
• Description: Monolithic 12-Bit Quad DAC
• Manufacturer: Analog Devices

Specifications of AD664

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Nibble,Par

REV.
Fully transparent operation can be thought of as a simultaneous
load of data from Figure 9a where replacing LS with TR causes
all 4 DACs to be loaded at once.
The Fully transparent mode is achieved by asserting lows on
QS0, QS1, QS2, TR and CS while keeping LS high in addition
to MS and RB. Figure 18a illustrates the necessary timing rela-
tionships. Fully transparent operation will also work with TR
tied low (enabled).
Partially transparent operation can be thought of as preloading
the first rank in Figure 10a without requiring the additional CS
pulse from Figure 11.
The partially transparent mode is achieved by setting CS, QS0,
QS1, QS2, LS, and TR low while keeping RD and MS high.
The address of the transparent DAC is asserted on DS0 and
DS1. Figure 19a illustrates the necessary timing relationships.
Partially transparent operation will also work with TR tied low
(enabled).
QS0, QS1, QS2
OUTPUT BITS
OUTPUT BITS
DATA INPUT/
DATA INPUT/
DS0, DS1, LS
D
Figure 19b. Partially Transparent Mode Timing
ADDRESS
Figure 18b. Fully Transparent Mode Timing
LS
QS
CS
TR
SYMBOL
t
t
t
t
t
t
t
SYMBOL
t
t
t
t
t
t
t
Figure 18a. Fully Transparent Mode
*FOR t
TR
CS
AS
QS
TS
TW
CH
DH
QH
DS
AS
TS
W
DH
AH
TH
1
INCREASED BY THE SAME AMOUNT THAT
t
TS
Figure 19a. Partially Transparent
*
IS GREATER THAN 0 ns.
TS
> 0, THE WIDTH OF TR MUST BE
t
DS
t
t
QS
25 C
MIN (ns)
0
0
0
80
90
0
0
25 C
MIN (ns)
0
0
0
90
15
15
15
TS
t
t
AS
t
TS
DS
ADDRESS VALID
t
TW
DATA VALID
DATA VALID
t
W
T
MIN (ns)
0
0
0
90
110
0
0
T
MIN (ns)
0
0
0
110
15
15
15
MIN
MIN
t
to T
to T
CH
t
MAX
MAX
AH
t
DH
t
DH
t
t
QH
TH
–11–
OUTPUT DATA
Two types of outputs may be obtained from the internal data
registers of the AD664 chip, mode select and DAC input code
data. Readback data may be in the same forms in which it can
be entered; 4-, 8-, and 12-bit wide words (12 bits only for
28-pin versions).
DAC Data Readback
DAC input code readback data is obtained by setting the address
of the DAC (DS0, DS1) and Quads (QS0, QS1, QS2) on the
address pins and bringing the RD and CS pins low. The timing
diagram for a DAC code readback operation appears in Figure 20.
Mode Data Readback
Mode data is read back in a similar fashion. By setting MS, QS0,
QS1, RD and CS low while setting TR and RST high, the mode
select word is presented to the I/O port pins. Figure 21 shows the
timing diagram for a readback of the mode select data register.
Figure 20b. DAC Input Code Readback Timing
Figure 21b. DAC Mode Readback Timing
Figure 20a. DAC Input Code Readback
SYMBOL
t
t
t
t
t
t
SYMBOL
t
t
t
t
t
t
AS
RS
DV
DF
AH
RH
AS
MS
DV
DF
AH
MH
Figure 21a. Mode Data Readback
25 C
MIN (ns)
0
0
150
60
0
0
25 C
MIN (ns)
0
0
150
60
0
0
T
MIN (ns)
0
0
180
75
0
0
T
MIN (ns)
0
0
180
75
0
0
MIN
MIN
to T
to T
MAX
MAX
AD664