ADA4505-4 Analog Devices, ADA4505-4 Datasheet - Page 14

• Manufacturer Part Number: ADA4505-4
• Description: 10 µA, Rail-to-Rail I/O, Zero Input Crossover Distortion Amplifiers
• Manufacturer: Analog Devices

Specifications of ADA4505-4

• Vcc-vee: 1.8V to 5V
• Isy Per Amplifier: 7µA
• Packages: CSP,SOP
• -3db Bandwidth: 50kHz
• Slew Rate: 6mV/µs
• Vos: 500µV
• Ib: 500fA
• # Opamps Per Pkg: 4
• Input Noise (nv/rthz): 65nV/rtHz

ADA4505-1/ADA4505-2/ADA4505-4
THEORY OF OPERATION
The ADA4505-1/ADA4505-2/ADA4505-4 are unity-gain stable
CMOS rail-to-rail input/output operational amplifiers designed
to optimize performance in current consumption, PSRR, CMRR,
and zero crossover distortion, all embedded in a small package.
The typical offset voltage is 500 μV, with a low peak-to-peak
voltage noise of 2.95 μV from 0.1 Hz to 10 Hz and a voltage
noise density of 65 nV/√Hz at 1 kHz.
The ADA4505-x amplifiers are designed to solve two key
problems in low voltage battery-powered applications: battery
voltage decrease over time and rail-to-rail input stage distortion.
In battery-powered applications, the supply voltage available to
the IC is the voltage of the battery. Unfortunately, the voltage of
a battery decreases as it discharges itself through the load. This
voltage drop over the lifetime of the battery causes an error in
the output of the op amps. Some applications requiring precision
measurements during the entire lifetime of the battery use voltage
regulators to power up the op amps as a solution. If a design
uses standard battery cells, the op amps experience a supply
voltage change from roughly 3.2 V to 1.8 V during the lifetime
of the battery. This means that for a PSRR of 70 dB minimum in
a typical op amp, the input-referred offset error is approximately
440 μV. If the same application uses the ADA4505-x with a 100 dB
minimum PSRR, the error is only 14 μV. It is possible to calibrate
this error out or to use an external voltage regulator to power
the op amp, but these solutions can increase system cost and
complexity. The ADA4505-x amplifiers solve the impasse with
no additional cost or error-nullifying circuitry.
The second problem with battery-powered applications is the
distortion caused by the standard rail-to-rail input stage. Using
a CMOS nonrail-to-rail input stage (that is, a single differential
pair) limits the input voltage to approximately one V
source voltage) away from one of the supply lines. Because V
for normal operation is commonly over 1 V, a single differential
pair, input stage op amp greatly restricts the allowable input
voltage range when using a low supply voltage. This limitation
restricts the number of applications where the nonrail-to-rail
input op amp was originally intended to be used. To solve this
problem, a dual differential pair input stage is usually implemented
(see Figure 53); however, this technique has its own drawbacks.
One differential pair amplifies the input signal when the common-
mode voltage is on the high end, whereas the other pair amplifies
the input signal when the common-mode voltage is on the low
end. This method also requires control circuitry to operate the
two differential pairs appropriately. Unfortunately, this topology
leads to a very noticeable and undesirable problem; if the signal
level moves through the range where one input stage turns off and
the other one turns on, noticeable distortion occurs (see Figure 54).
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This distortion forces the designer to devise impractical ways
to avoid the crossover distortion areas, thereby narrowing the
common-mode dynamic range of the operational amplifier. The
ADA4505-x family solves this crossover distortion problem by
using an on-chip charge pump to power the input differential
pair. The charge pump creates a supply voltage higher than the
voltage of the battery, allowing the input stage to handle a wide
range of input signal voltages without using a second differential
pair. With this solution, the input voltage can vary from one
supply extreme to the other with no distortion, thereby restoring
the full common-mode dynamic range of the op amp.
The charge pump has been carefully designed so that switching
noise components at any frequency, both within and beyond the
amplifier bandwidth, are much lower than the thermal noise floor.
Therefore, the spurious-free dynamic range (SFDR) is limited
only by the input signal and the thermal or flicker noise. There
is no intermodulation between input signal and switching noise.
(Dual PMOS Q1 and Q2 Transistors Form the Lower End of the Input Voltage
Response in a Dual Differential Pair Input Stage Op Amp (Powered by a 5 V
Supply; Results of Approximately 100 Units per Graph Are Displayed)
Figure 54. Typical Input Offset Voltage vs. Common-Mode Voltage
I
V
B
Range; Dual NMOS Q3 and Q4 Transistors Form the Upper End)
–100
–150
–200
–250
–300
IN+
300
250
200
150
100
–50
Figure 53. Typical Dual Differential Pair Input Stage Op Amp
50
0
V
0
SS
Q3
V
T
0.5
SY
A
= 25°C
= 5V
Q1
1.0
1.5
Q2
2.0
V
CM
V
Q4
2.5
DD
(V)
3.0
V
IN–
I
B
3.5
4.0
4.5
V
BIAS
5.0