AD8044 Analog Devices, AD8044 Datasheet - Page 13

• Manufacturer Part Number: AD8044
• Description: Quad 150 MHz Rail-to-Rail Amplifier
• Manufacturer: Analog Devices

Specifications of AD8044

• -3db Bandwidth: 160MHz
• Slew Rate: 190V/µs
• Vos: 1.4mV
• Ib: 2µA
• # Opamps Per Pkg: 4
• Input Noise (nv/rthz): 16nV/rtHz
• Vcc-vee: 3V to 12V
• Isy Per Amplifier: 3.4mA
• Packages: DIP,SOIC

REV. B
Active Filters
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
Figure 38 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8044 package. Such
circuits are sometimes used in medical ultrasound systems to
lower the noise bandwidth of the analog signal before A/D
conversion.
The frequency response of the circuit is shown in Figure 39.
Figure 38. 2 MHz Biquad Band-pass Filter Using AD8044
Figure 39. Frequency Response of 2 MHz Band-pass
Biquad Filter
V
IN
–10
–20
–30
–40
3k
R1
0
10k
2
3
50pF
AD8044
2k
C1
R2
100k
1
2k
R3
FREQUENCY (Hz)
6
5
AD8044
2k
1k
R6
R4
1M
7
2k
R5
10
10M
9
50pF
AD8044
C2
8
100M
V
OUT
–13–
Layout Considerations
The specified high speed performance of the AD8044 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large (0.47 mF
– 10 mF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 W or 75 W and properly termi-
nated at each end.
AD8044