ADM8691 Analog Devices, ADM8691 Datasheet - Page 16

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ADM8691

Manufacturer Part Number
ADM8691
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADM8691

Product Description
µP Supv w/ Backup Batt Switch, Adj Reset Period, Adj Watchdog Period, 4.65V Trip point, 100 mA Iout
Supply Current
200µA
Us Price 1000-4999
n/a
Display In Ist
Yes
Active For Param Search
Yes

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ADM8690/ADM8691/ADM8695
ALTERNATE WATCHDOG INPUT DRIVE CIRCUITS
The watchdog feature can be enabled and disabled under
program control by driving WDI with a three-state buffer (see
Figure 28). When three-stated, the WDI input floats, thereby
disabling the watchdog timer.
This circuit is not entirely foolproof, and it is possible for a
software fault to erroneously three-state the buffer, preventing
the
microprocessor is no longer operating correctly. In most cases,
a better method is to extend the watchdog period rather than
disable the watchdog.
ADM8690/ADM8691/ADM8695
WATCHDOG
CONTROL
Figure 28. Enabling and Disabling the Watchdog Input
STROBE
INPUT
WDI
from detecting that the
ADM8690/
ADM8691/
ADM8695
Rev. C | Page 16 of 24
For the ADM8691/ADM8695, the watchdog period can be
extended under program control using the circuit shown in
Figure 29. When the control input is high, the OSC SEL pin is
low and the watchdog timeout is set by the external capacitor.
A 0.01 μF capacitor sets a watchdog timeout delay of 100 sec.
When the control input is low, the OSC SEL pin is driven high,
selecting the internal oscillator. The 100 ms or the 1.6 sec
period is chosen, depending on which diode is used, as shown
in Figure 29. With D1 inserted, the internal timeout is set to
100 ms; with D2 inserted, the timeout is set to 1.6 sec.
CONTROL
INPUT
1
Figure 29. Extending the Watchdog Period
D1
D2
1
HIGH = EXTERNAL TIMEOUT
LOW = INTERNAL TIMEOUT
OSC SEL
OSC IN
ADM8691/
ADM8695
Data Sheet

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