ADM8696 Analog Devices, ADM8696 Datasheet - Page 10

• Manufacturer Part Number: ADM8696
• Manufacturer: Analog Devices

Specifications of ADM8696

• Batt-backup-flg: Yes
• Product Description: µP Supv w/ Backup Batt Switch, Adj Low Line V Monitor, Adj Watchdog Timer, Pwr Fail& Watchdog Status
• Reset Threshold (v): 1.3
• Min Reset Timeout (ms): 35 (Adjustable)
• Reset Output-stage: Active-High/Push-Pull,Active-Low/Push-Pull
• Backup-battery Switch: Yes
• Chip Enable Gating: ---
• Typ Watchdog Timeout (ms): 100,1600,adj.
• Package: DIP,SOIC,SOP
• Us Price 1000-4999: n/a

ADM8696/ADM8697
TYPICAL APPLICATIONS
ADM8696
Figure 18 shows the ADM8696 in a typical power monitoring,
battery backup application. V
Under normal operating conditions with V
internally connected to V
decay and V
power for the CMOS RAM.
Power Fail RESET
The V
put, LL
1.3 V. RESET will remain low for 50 ms after LL
above 1.3 V. This allows for a power-on reset and prevents re-
peated toggling of RESET if the V
Resistors R3 and R4 should be chosen to give the desired V
reset threshold.
Watchdog Timer
The Watchdog Timer Input (WDI) monitors an I/O line from
the P system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the P system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age V
RESET threshold so there is sufficient time available to com-
plete the shutdown procedure before the processor is RESET
and power is lost.
Figure 18a. ADM8696 Typical Application Circuit A
RESET
T
CC
. The threshold should be set at a higher voltage than the
+5V
IN
power supply is also monitored by the Low Line In-
. A RESET pulse is generated when LL
OUT
BATTERY
will be switched to V
R4
R3
+
R1
R2
CC
LL
. If a power failure occurs, V
PFI
V
ADM8696
BATT
IN
OUT
GND
V
CC
powers the CMOS RAM.
CC
RESET
V
PFO
WDI
BATT
power supply is unstable.
OUT
, thereby maintaining
CC
present, V
CMOS RAM
POWER
I/O LINE
P RESET
P NMI
IN
P SYSTEM
IN
P POWER
falls below
returns
OUT
CC
will
CC
is
–10–
Figure 18b shows a similar application for the ADM8696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
This application also shows an optional external transistor that
may be used to provide in excess of 100 mA current on V
When V
low, providing 25 mA of base drive for the external PNP transis-
tor. The maximum current available is dependent on the power
rating of the external transistor.
RAM Write Protection
The ADM8697 CE
CMOS RAM. CE
reset threshold. If LL
goes high, independent of the logic level at CE
the microprocessor from writing erroneous data into RAM dur-
ing power-up, power-down, brownouts and momentary power
interruptions.
POWER
INPUT
R2
R1
Figure 18b. ADM8696 Typical Application Circuit B
CC
7805
is higher than V
R3
R4
BATTERY
OUT
OUT
RESET
IN
3V
NC
follows CE
line drives the Chip Select inputs of the
falls below the reset threshold, CE
0.1 F
BATT
V
GND
OSC IN
OSC SEL
PFI
LL
LOW LINE
BATT
V
SYSTEM STATUS
IN
CC
ADM8696
INDICATORS
, the BATT ON output goes
IN
BATT
ON
as long as LL
WDO
RESET
V
OUT
PFO
WDI
0.1 F
IN
CMOS RAM
. This prevents
I/O LINE
NMI
RESET
IN
A0–A15
V
CC
is above the
REV. A
POWER
OUT
OUT
P
P
.