ADP1650 Analog Devices, ADP1650 Datasheet - Page 6

• Manufacturer Part Number: ADP1650
• Description: 1.5 A LED Flash Driver with I2C-Compatible Interface
• Manufacturer: Analog Devices

Specifications of ADP1650

• Product Description: 1.5 A LED Flash Driver with I2C-Compatible Interface
• Led #: 1
• Led Configuration: Serial
• Topology: Inductive
• Application: Flash
• I2c Support: Yes
• Max Iout (ma): 1500mA
• Brightness Control: I2C
• Peak Efficiency (%): 90%
• Switching Frequency: 3MHz
• Over Volt Protection (v): 5.5V
• Vin Min (v): 2.7V
• Vout (v): 4.575 to 5.425
• Synchronous: Yes
• Package: 12-Bump WLCSP

ADP1650
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN, SDA, SCL, EN, GPIO1, GPIO2, STROBE,
PGND to SGND
Ambient Temperature Range (T
Junction Temperature Range (T
Storage Temperature
ESD Human Body Model
ESD Charged Device Model
ESD Machine Model
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
The ADP1650 may be damaged if the junction temperature
limits are exceeded. Monitoring T
is within the specified temperature limits. In applications with
high power dissipation and poor thermal resistance, the maximum
T
dissipation and low PCB thermal resistance, the maximum T
can exceed the maximum limit as long as the T
fication limits. T
dissipation (PD) of the device, and the junction-to-ambient
thermal resistance (θ
calculated from the T
A
LED_OUT, SW, VOUT to Power Ground
may have to be derated. In applications with moderate power
T
J
= T
A
+ (PD × θ
J
of the device is dependent on the T
JA
A
JA
) of the package. Maximum T
and PD using the following formula:
)
A
J
)
)
A
does not guarantee that T
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
±2000 V
±500 V
±150 V
J
is within speci-
A
, the power
J
is
A
Rev. C | Page 6 of 32
J
THERMAL RESISTANCE
θ
a 4-layer board. θ
board layout. In applications where high maximum power dissi-
pation exists, attention to thermal board design is required. The
value of θ
environmental conditions. The specified value of θ
on a 4-layer, 4 in × 3 in, 2 ½ oz copper board, per JEDEC
standards. For more information, see the
Note, MicroCSP™ Wafer Level Chip Scale Package.
θ
Table 5. Thermal Resistance
Package Type
12-Ball WLCSP
10-Lead LFCSP
ESD CAUTION
JA
JA
of the package is based on modeling and calculation using
is specified for a device mounted on a JEDEC 2S2P PCB.
JA
may vary, depending on PCB material, layout, and
JA
is highly dependent on the application and
θ
75
42.5
JA
AN-617
Application
JA
Unit
°C/W
°C/W
is based