ADP151 Analog Devices, ADP151 Datasheet - Page 5

• Manufacturer Part Number: ADP151
• Description: Ultra Low Noise, 200 mA CMOS Linear Regulator
• Manufacturer: Analog Devices

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP151 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
The maximum junction temperature (T
ambient temperature (T
formula
The junction-to-ambient thermal resistance (θ
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
T
J
= T
A
+ (P
D
× θ
JA
)
A
) and power dissipation (P
J
is within the specified temperature
D
), and the junction-to-ambient
JA
).
JA
J
) is calculated from the
may vary, depending
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to +6.5V
−65°C to +150°C
−40°C to +125°C
−40°C to +125°C
JEDEC J-STD-020
JA
) of the package
D
) using the
A
), the
J
) of
Rev. D | Page 5 of 24
on PCB material, layout, and environmental conditions. The
specified values of θ
board. See JESD51-7 and JESD51-9 for detailed information
on the board construction. For additional information, see the
AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale
Package, available at www.analog.com.
Ψ
with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
6-Lead 2 mm × 2 mm LFCSP
ESD CAUTION
JA
JB
and Ψ
is the junction-to-board thermal characterization parameter
T
J
= T
JB
.
JB
B
are specified for the worst-case conditions, that is, a
+ (P
D
× Ψ
JA
JB
JB
JB
are based on a 4-layer, 4 in. × 3 in. circuit
. Therefore, Ψ
JB
)
of the package is based on modeling and
measures the component power flowing
B
) and power dissipation (P
JB
more useful in real-world
JB
thermal paths include
θ
170
260
63.6
JA
J
Ψ
43
58
28.3
) is calculated
JB
ADP151
Unit
°C/W
°C/W
°C/W
D
)