ADP1873 Analog Devices, ADP1873 Datasheet

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ADP1873

Manufacturer Part Number
ADP1873
Description
Synchronous Current-Mode Buck Controller with Constant On-time, 0.6 V Reference Voltage, and Power Saving Mode
Manufacturer
Analog Devices
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADP1873ARMZ-0.3-R7
Manufacturer:
Analog Devices Inc
Quantity:
1 900
FEATURES
Power input voltage as low as 2.75 V to 20 V
Bias supply voltage range: 2.75 V to 5.5 V
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 KHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1873 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
140 μA shutdown supply current
Starts into a precharged load
Small, 10-lead MSOP package
APPLICATIONS
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
GENERAL DESCRIPTION
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current-
mode control architecture. This allows the ADP1872/ADP1873
to drive all N-channel power stages to regulate output voltages
as low as 0.6 V.
The ADP1873 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1873)
section for more information).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Constant On-Time, PWM Buck Controller
Synchronous Current-Mode with
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are
well suited for a wide range of applications. These ICs not only
operate from a 2.75 V to 5.5 V bias supply, but can also accept a
power input as high as 20 V.
In addition, an internally fixed, soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a pre-
charged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1872/ADP1873 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP.
Figure 2. ADP1872 Efficiency vs. Load Current (V
V
V
OUT
100
DD
95
90
85
80
75
70
65
60
55
50
45
100
TO 5.5V
= 2.75V
R
C
V
R
C
C
TYPICAL APPLICATIONS CIRCUIT
C
DD
C
TOP
VDD2
R
VDD
BOT
= 5.5V, V
C
V
C2
DD
©2009–2010 Analog Devices, Inc. All rights reserved.
= 5.5V, V
IN
COMP/EN
FB
GND
VDD
= 5.5V (PSM)
ADP1872/
ADP1873
ADP1872/ADP1873
1k
PGND
LOAD CURRENT (mA)
IN
VIN
V
= 16.5V (PSM)
DD
Figure 1.
T
V
f
WURTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
SW
DRVH
DRVL
A
OUT
= 5.5V, V
BST
= 25°C
SW
= 300kHz
= 1.8V
IN
V
C
R
= 13.0V (PSM)
IN
RES
BST
10k
V
= 2.75V TO 20V
DD
C
IN
= 5.5V, V
OUT
Q1
Q2
= 1.8 V, 300 kHz)
C
www.analog.com
L
OUT
IN
LOAD
= 5.5V
+
V
5A
OUT
100k

Related parts for ADP1873

ADP1873 Summary of contents

Page 1

... This allows the ADP1872/ADP1873 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. The ADP1873 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1873) section for more information) ...

Page 2

... Undervoltage Lockout ............................................................... 18 Thermal Shutdown ..................................................................... 18 Programming Resistor (RES) Detect Circuit .......................... 19 Valley Current-Limit Setting .................................................... 19 Hiccup Mode During Short Circuit ......................................... 20 Synchronous Rectifier ................................................................ 21 Power Saving Mode (PSM) Version (ADP1873) .................... 21 REVISION HISTORY 3/10—Rev Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Figure 59 Caption and Figure 60 Caption .............. 16 Changes to Figure 64 ...

Page 3

... Conditions ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz μF to PGND 0.22 μF to GND IN IN ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz 1 switching Q_BST + I COMP/EN < 285 mV BST, SD Rising VDD (See Figure 34 for temperature variation) ...

Page 4

... ADP1872/ADP1873 Parameter Symbol OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time Fall Time t Low-Side Driver Output Source Resistance Output Sink Resistance 2 Rise Time t 2 Fall Time t Propagation Delays 2 DRVL Fall to DRVH Rise t DRVH Fall to DRVL Rise ...

Page 5

... Table 3. Thermal Resistance Package Type θ (10-Lead MSOP) JA 2-Layer Board 4-Layer Board BOUNDARY CONDITION In determining the values given in Table 2 and Table 3, natural convection was used to transfer heat to a 4-layer evaluation board. ESD CAUTION Rev Page ADP1872/ADP1873 θ Unit JA 213.1 °C/W 171.7 °C/W ...

Page 6

... Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations Section). 5 VDD Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended. 6 DRVL Drive Output for the External Lower Side, N-Channel MOSFET ...

Page 7

... Figure 6. Efficiency—300 kHz 5.5V 5. 5.5V IN 10k 100k = 0.8 V OUT V = 5.5V 5. 10k 100k = 1.8 V OUT V = 5.5V DD 13V IN IN 16. 10k 100k = 7 V OUT Rev Page ADP1872/ADP1873 100 V = 5.5V 13V (PSM 5.5V 5. 5.5V 5.5V (PSM 5.5V 3.6V 16. 5.5V 13V ...

Page 8

... ADP1872/ADP1873 100 V = 5.5V 13V (PSM 5.5V 5.5V 5.5V (PSM 5.5V 16. (PSM 5.5V 5.5V 13V 3.6V 5. 3.6V 3. WURTH IND: 744303012 0.12µH, DCR: 0.33mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER 25°C ...

Page 9

... Figure 20. Output Voltage Accuracy—1.0 MHz, V OUT 0.6030 0.6025 0.6020 0.6015 0.6010 0.6005 0.6000 0.5995 0.5990 0.5985 0.5980 0.5975 –40.0 = 0.8 V OUT Rev Page ADP1872/ADP1873 13V V = 16. +125°C +125°C +125°C +25°C +25°C +25°C –40°C –40°C – ...

Page 10

... ADP1872/ADP1873 335 V = 5.5V +125°C DD +25°C 325 V = 3.6V DD –40°C 315 305 295 285 275 265 255 245 235 225 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 V (V) IN Figure 22. Switching Frequency vs. High Input Voltage, 300 kHz, ±10 650 V = 5.5V +125°C DD +25° 3.6V DD –40°C 600 550 ...

Page 11

... V OUT 1450 1400 1350 1300 1250 1200 1150 1100 1050 1000 8000 8800 9600 Figure 33. Frequency vs. Load Current, 1.0 MHz, V OUT Rev Page ADP1872/ADP1873 V = 5.5V +125°C IN +25° 13V IN –40° 16.5V IN 2000 4000 6000 8000 10,000 12,000 14,000 LOAD CURRENT (mA ...

Page 12

... ADP1872/ADP1873 2.658 2.657 2.656 2.655 2.654 2.653 2.652 2.651 2.650 2.649 –40 – TEMPERATURE (°C) Figure 34. UVLO vs. Temperature 100 300 400 500 600 700 FREQUENCY (kHz) Figure 35. Maximum Duty Cycle vs. Frequency ...

Page 13

... 4.7 5.1 5.5 DD +125°C +25°C 4 –40° 4.7 5.1 5.5 (Low Input Voltage) DD Rev Page ADP1872/ADP1873 OUTPUT VOLTAGE INDUCTOR CURRENT SW NODE LOW SIDE B CH1 50mV CH2 5A Ω M400ns A CH2 W B CH3 10V CH4 5V T 35.8% W OUTPUT VOLTAGE INDUCTOR CURRENT SW NODE LOW SIDE ...

Page 14

... ADP1872/ADP1873 OUTPUT VOLTAGE 2 20A STEP CH1 10A Ω CH2 200mV M2ms W CH3 20V CH4 5V T 75.6% Figure 46. Load Transient Step—PSM Enabled (See Figure 91 Application Circuit) OUTPUT VOLTAGE 2 20A POSITIVE STEP SW NODE 1 3 LOW SIDE 4 B CH1 10A Ω ...

Page 15

... LOW SIDE 4 SW NODE 3 INDUCTOR CURRENT 2 720mV B CH1 CH3 10V Figure 57. Soft Start and RES Detect Waveform Rev Page ADP1872/ADP1873 OUTPUT VOLTAGE INDUCTOR CURRENT LOW SIDE SW NODE CH2 5A Ω M4ms A CH1 720mV CH4 5V T 41.6% OUTPUT VOLTAGE INDUCTOR CURRENT SW NODE ...

Page 16

... ADP1872/ADP1873 T = 25°C LOW SIDE MINUS SW CH2 5V M40ns CH3 5V CH4 2V T 29.0% MATH 2V 40ns Figure 58. Output Drivers and SW Node Waveforms t 16ns ( LOW SIDE f , DRVL t 22ns ( ) 4 pdh , DRVH 25ns ( SW NODE MINUS M SW CH2 5V M40ns CH3 5V CH4 2V T 29.0% MATH 2V 40ns Figure 59 ...

Page 17

... SS_REF ERROR AMP 0.6V PWM I REV COMP V REG CS LOWER AMP COMP CLAMP ADC REF_ZERO CS GAIN SET GND Figure 64. ADP1872/ADP1873 Block Diagram Rev Page ADP1872/ADP1873 ADP1872/ TO ENABLE ADP1873 ALL BLOCKS VIN FILTER V DD BST DRVH DRIVERS SW DRVL PGND 800kΩ CS GAIN PROGRAMMING ...

Page 18

... ADP1873 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. STARTUP The ADP1872/ADP1873 have an input low voltage pin (VDD) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VDD (Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence is ...

Page 19

... Open 12 100 kΩ 24 VALLEY CURRENT-LIMIT SETTING The architecture of the ADP1872/ADP1873 is based on valley current-mode control. The current limit is determined by three components: the R output voltage swing (COMP), and the current-sense gain. The COMP range is internally fixed at 1.4 V. The current-sense gain is programmable via an external resistor at the DRVL pin (see the Programming Resistor (RES) Detect Circuit section) ...

Page 20

... ADP1872/ADP1873 Table 6. Valley Current Limit Program Valley Current Level 47 kΩ 22 kΩ Open R ON (mΩ V V 1.5 2 2.5 3 39.0 3.5 33.4 4.5 26.0 5 23.4 5.5 21.25 10 23.3 11.7 15 31.0 15.5 7.75 18 26.0 13.0 6.5 1 Refer to Figure 70 for more information and a graphical representation RES = NO RES 12V ...

Page 21

... MOSFETs or reduce efficiency as a result of excessive power loss. POWER SAVING MODE (PSM) VERSION (ADP1873) The power saving mode version of the ADP1872 is the ADP1873. The ADP1873 operates in the discontinuous conduction mode (DCM) and pulse skips at light load to midload currents. It outputs pulses as necessary to maintain output regulation ...

Page 22

... In this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. OUT Because the ADP1872/ADP1873 has the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent ...

Page 23

... ESR is the equivalent series resistance of the output capacitors calculate the output load step, use the following equation: where ΔV a given positive load current step (ΔI Rev Page ADP1872/ADP1873 DCR I Dimensions SAT (mΩ) (A) (mm) Manufacturer 0.33 55 10.2 × 7 Wü ...

Page 24

... MLCCs should be mounted in parallel to reduce the overall series resistance. COMPENSATION NETWORK Due to its current-mode architecture, the ADP1872/ADP1873 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values necessary to examine the converter’s overall loop ...

Page 25

... TOTAL The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression × N2 (ON) LOAD BIAS ) DD Rev Page ADP1872/ADP1873 300 400 500 600 700 800 FREQUENCY (kHz × ...

Page 26

... Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses recommended to use shielded ferrite core material type inductors with the ADP1872/ADP1873 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (EMI). ...

Page 27

... MOSFETs, and does not re-enable until the junction temperature cools to 140°C (see the Thermal Shutdown section). The maximum junction temperature allowed for the ADP1872/ ADP1873 ICs is 125°C. This means that the sum of the ambient temperature (T ) and the rise in package temperature ( caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125° ...

Page 28

... ADP1872/ADP1873 The inductor peak current is approximately × 0.5) = 17.5 A Therefore, an appropriate inductor selection is 1.0 μH with DCR = 3.3 mΩ (7443552100) from Table 7 with peak current handling × DCR I DCR ( LOSS ) LOAD 2 = 0.003 × ( 675 mW Current Limit Programming The valley current is approximately 15 A − ...

Page 29

... P ] × N2(ON) LOAD 1.215 W + 151 534 77. × 3. 675 mW + 56. 2.62 W Rev Page ADP1872/ADP1873 = f × R × C × I × VIN × (LOSS) SW GATE TOTAL LOAD 3 −9 × 1.5 Ω × 3.3 × 10 × × 12 × × ...

Page 30

... ADP1872/ADP1873 EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 8 are with and a maximum load current The ADP1873 models listed in Table 8 are the PSM versions of the device. Table 8. External Component Values Marking Code SAP Model ADP1872 ADP1872ARMZ-0.3-R7/ LDT ADP1873ARMZ-0.3-R7 ...

Page 31

... Package 30 3.2 20 PG-TDSON8 30 1.6 10 PG-TDSON8 30 35 SO-8 30 2.4 25 SO-8 30 3.2 20 PG-TDSON8 30 1.6 10 PG-TDSON8 30 35 SO-8 Rev Page ADP1872/ADP1873 COMP C (μF) (μH) (kΩ) (pF) OUT 6 3 × 47 1.0 34 268 1.0 34 228 Manufacturer Model Number Würth Elektronik 744303012 Würth Elektronik 744303022 Würth Elektronik 744355147 Wü ...

Page 32

... C2 C1 0.1µF 1µF Figure 82. ADP1872/ADP1873 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths) Figure 82 shows the schematic of a typical ADP1872/ADP1873 used for a high power application. Blue traces denote high current pathways. VIN, PGND, and V possibly replicated, descending down into the multiple layers. ...

Page 33

... POSSIBLE TO THE IC. INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4. Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board SW Rev Page ADP1872/ADP1873 OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS ...

Page 34

... ADP1872/ADP1873 Figure 84. Layer 2 of Evaluation Board Rev Page ...

Page 35

... VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 82). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 86, LAYER 4 FOR PGND TAP). Figure 85. Layer 3 of Evaluation Board Rev Page ADP1872/ADP1873 ...

Page 36

... ADP1872/ADP1873 BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84. Figure 86. Layer 4 (Bottom Layer) of Evaluation Board Rev Page ...

Page 37

... Figure 87. Primary Current Pathways During the On State of the Upper-Side MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow) DIFFERENTIAL SENSING Because the ADP1872/ADP1873 operate in valley current- mode control, a differential voltage reading is taken across the drain and source of the lower-side MOSFET. The drain of the lower-side MOSFET should be connected as close as possible to the SW pin (Pin 9) of the IC ...

Page 38

... Q3 Q4 GND PGND 4 7 VDD DRVL 5 6 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) R5 100kΩ PANASONIC: (OUTPUT CAPACITORS) INFINEON MOSFETs: WURTH INDUCTORS: HIGH VOLTAGE INPUT VIN = 5.5V ADP1872/ C12 ADP1873 100nF VIN BST COMP/ DRVH GND PGND ...

Page 39

... MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) BSC080N03MS G (UPPER-SIDE) WURTH INDUCTORS: 0.72µH, 1.65mΩ, 35A 744325072 Rev Page ADP1872/ADP1873 22µF 22µF 22µF 22µF 22µ ...

Page 40

... ADP1873ARMZ-0.6-R7 −40°C to +125°C ADP1873ARMZ-1.0-R7 −40°C to +125°C ADP1873ARMZ-0.3-EVALZ ADP1873ARMZ-0.6-EVALZ ADP1873ARMZ-1.0-EVALZ RoHS Compliant Part. ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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