ADAV4622 Analog Devices, ADAV4622 Datasheet - Page 24

• Manufacturer Part Number: ADAV4622
• Description: Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder
• Manufacturer: Analog Devices

Specifications of ADAV4622

• Instructions/cycles: 2560
• Dac Dnr (db): 94dB
• Dac Thd+n: 86dB
• Product Description: Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder

ADAV4622
LRCLK
LRCLK
PWM OUTPUTS
In the ADAV4622, the main outputs are available as four PWM
output channels, which are suitable for driving Class-D amplifiers.
PWM_Ready is a status pin used to signify that the ADAV4622
PWM outputs are in a valid state. During PWM power-up and
power-down, this pin remains low to signify that the outputs
are not in a valid state. The output power stage should remain
muted until this pin goes high. This functionality helps to
eliminate pop/click and other unwanted noise on the outputs.
Each set of PWM outputs is a complementary output. The
modulation frequency is 384 kHz, and the full-scale duty cycle
has a ratio of 97:3.
Full details on the use of the PWM outputs are available upon
request. Contact a local Analog Devices sales representative for
more details.
LRCLK
BCLK
BCLK
SDO0
BCLK
SDO0
SDO0
MSB
Figure 29. PWM Output Section
MODULATOR
MODULATOR
MODULATOR
MODULATOR
MSB
PWM
PWM
PWM
PWM
MSB
LEFT CHANNEL
LEFT CHANNEL
+
–
+
–
+
–
+
–
LEFT CHANNEL
PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM4A
PWM4B
PWM_READY
LSB
LSB
Figure 28. Right-Justified Mode
Figure 27. Left-Justified Mode
Rev. B | Page 24 of 28
Figure 26. I
LSB
1 /F
1 /F
S
1 /F
2
S Mode
S
S
MSB
HEADPHONE OUTPUTS
There are two stereo headphone amplifier outputs capable
of driving 32 Ω loads at 1 V rms. HPOUT1 is shared with
AUXOUT4, and HPOUT2 is shared with AUXOUT2, as shown
in Figure 30.
I
One I
inputs, which are BCLK1 and LRCLK1 by default. If an addi-
tional digital output is required, an additional pin can be
reconfigured as a serial digital output, as shown in Figure 31.
2
S DIGITAL AUDIO OUTPUTS
2
S output, SDO0, uses the same serial clocks as the serial
MSB
L
R
L
R
I
INTERFACE
Figure 30. Headphone Outputs Section
2
S OUTPUT
RIGHT CHANNEL
LRCLK1
MSB
BCLK1
RIGHT CHANNEL
DAC
DAC
Figure 31. I
RIGHT CHANNEL
OUTPUT
2
S/PDIF
S Digital Outputs
PA
PA
AUXOUT4L
AUXOUT4R
AUXOUT2L
AUXOUT2R
LSB
LSB
HPOUT1L
HPOUT1R
HPOUT2L
HPOUT2R
SDO0
SPDIF_OUT (SDO1)
LSB