LPC2420_60 NXP Semiconductors, LPC2420_60 Datasheet - Page 59
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LPC2420_60
Manufacturer Part Number
LPC2420_60
Description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded trace
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2420_60.pdf
(86 pages)
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Table 14.
C
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
CSLAV
OELAV
CSLOEL
am
h(D)
CSHOEH
OEHANV
OELOEH
BLSLAV
CSHBLSH
CSLWEL
CSLBLSL
WELDV
CSLDV
WELWEH
BLSLBLSH
WEHANV
L
= 30 pF, T
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
BLS LOW to address valid
time
CS HIGH to BLS HIGH time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH
time
WE HIGH to address invalid
time
Dynamic characteristics: Static external memory interface
amb
11.4 Static external memory interface
=
40
C to 85
[1][2]
[1][6]
C, V
[1]
DD(DCDC)(3V3)
Conditions
= V
DD(3V3)
[3][4]
[5]
[3]
[3]
[3]
= 3.0 V to 3.6 V.
Min
0.29
0.29
0.78 + T
(WAITRD WAITOEN + 1)
T
0
0.49
0.20
0.59 + (WAITRD
WAITOEN + 1) T
0.39
0.88
0.88 + T
WAITWEN)
0.88
0.68
0
0.78 + T
(WAITWR WAITWEN + 1)
0.88 + T
(WAITWR WAITWEN + 3)
0 + T
cy(CCLK)
cy(CCLK)
12.70
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
WAITOEN 0 + T
(1 +
cy(CCLK)
Typ
0.20
0.20
(WAITRD WAITOEN + 1)
T
-
0
0.20
0 + (WAITRD WAITOEN +
1) T
0
0.49
0.10 + T
WAITWEN)
0.49
2.54
2.64
0 + T
WAITWEN + 1)
0 + T
WAITWEN + 3)
0.20 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
9.57
WAITOEN
(WAITWR
(WAITWR
(1 +
2.54
2.54
0.49 + T
2.44
2.54
WAITWEN)
(WAITWR WAITWEN + 1)
(WAITWR WAITWEN + 3)
Max
(WAITRD WAITOEN + 1)
T
-
0.20
0.10 + (WAITRD
WAITOEN + 1) T
0.68
0.20 + T
0.98
5.86
4.79
0.10 + T
0.59 + T
2.74 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
8.11
WAITOEN
(1 +
cy(CCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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